From 303980c502c721f13d65e7087be6c0758df65044 Mon Sep 17 00:00:00 2001
From: Sadik Armagan <sadik.armagan@arm.com>
Date: Fri, 17 Apr 2020 12:45:14 +0100
Subject: IVGCVSW-4668 Add TENSOR_QUANT8_ASYMM_SIGNED data type support to
 CpuRef operators

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
Change-Id: I094125ba80699cc3cf5226bda6662a54e6caa988
---
 src/backends/reference/RefWorkloadFactory.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/backends/reference/RefWorkloadFactory.cpp')

diff --git a/src/backends/reference/RefWorkloadFactory.cpp b/src/backends/reference/RefWorkloadFactory.cpp
index 5d3775a59d..4566fe5e40 100644
--- a/src/backends/reference/RefWorkloadFactory.cpp
+++ b/src/backends/reference/RefWorkloadFactory.cpp
@@ -468,6 +468,10 @@ std::unique_ptr<IWorkload> RefWorkloadFactory::CreatePad(const PadQueueDescripto
     {
         return std::make_unique<RefPadBFloat16Workload>(descriptor, info);
     }
+    else if (IsQAsymmS8(info))
+    {
+        return std::make_unique<RefPadQAsymmS8Workload>(descriptor, info);
+    }
     return MakeWorkload<RefPadFloat32Workload, RefPadQAsymm8Workload>(descriptor, info);
 }
 
@@ -482,6 +486,10 @@ std::unique_ptr<IWorkload> RefWorkloadFactory::CreatePermute(const PermuteQueueD
     {
         return std::make_unique<RefPermuteBFloat16Workload>(descriptor, info);
     }
+    else if (IsQAsymmS8(info))
+    {
+        return std::make_unique<RefPermuteQAsymmS8Workload>(descriptor, info);
+    }
     return MakeWorkloadHelper<RefPermuteFloat16Workload, RefPermuteFloat32Workload, RefPermuteQAsymm8Workload,
         NullWorkload, NullWorkload, NullWorkload>(descriptor, info);
 }
@@ -603,6 +611,10 @@ std::unique_ptr<IWorkload> RefWorkloadFactory::CreateTranspose(const TransposeQu
     {
         return std::make_unique<RefTransposeBFloat16Workload>(descriptor, info);
     }
+    else if (IsQAsymmS8(info))
+    {
+        return std::make_unique<RefTransposeQAsymmS8Workload>(descriptor, info);
+    }
     return MakeWorkloadHelper<RefTransposeFloat16Workload, RefTransposeFloat32Workload, RefTransposeQAsymm8Workload,
             NullWorkload, NullWorkload, NullWorkload>(descriptor, info);
 }
-- 
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