From e2af6f4322a1e2b8b3c391fb721a6a80c281477f Mon Sep 17 00:00:00 2001 From: Narumol Prangnawarat Date: Fri, 28 Jan 2022 17:59:18 +0000 Subject: IVGCVSW-6552 Add support of aligned host memory * Add AllocatedData functions to OutputHandler * Enable import aligned memory in ImportInputs * Enable import aligned memory in ImportOutputs * Allow to import input and output if the memory is aligned * Implement Reconfigure function on ClConvolution2dWorkload * End-to-end test on Ref and Cl to ensure that input and output memory are imported when aligned Signed-off-by: Narumol Prangnawarat Change-Id: I9e5e4c26d1ac2f1d806803ade5f64c6479c51718 --- src/armnn/LoadedNetwork.hpp | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'src/armnn/LoadedNetwork.hpp') diff --git a/src/armnn/LoadedNetwork.hpp b/src/armnn/LoadedNetwork.hpp index 9de6307938..f637dec8eb 100644 --- a/src/armnn/LoadedNetwork.hpp +++ b/src/armnn/LoadedNetwork.hpp @@ -55,14 +55,18 @@ public: TensorInfo GetInputTensorInfo(LayerBindingId layerId) const; TensorInfo GetOutputTensorInfo(LayerBindingId layerId) const; - std::vector ImportInputs(const InputTensors& inputTensors); - std::vector ImportOutputs(const OutputTensors& outputTensors); + std::vector ImportInputs(const InputTensors& inputTensors, + MemorySource forceImportMemorySource = MemorySource::Undefined); + std::vector ImportOutputs(const OutputTensors& outputTensors, + MemorySource forceImportMemorySource = MemorySource::Undefined); void ClearImportedInputs(const std::vector inputIds); void ClearImportedOutputs(const std::vector outputIds); /// Single thread execution of the loaded network - Status EnqueueWorkload(const InputTensors& inputTensors, const OutputTensors& outputTensors); + Status EnqueueWorkload(const InputTensors& inputTensors, const OutputTensors& outputTensors, + std::vector preImportedInputIds = {}, + std::vector preImportedOutputIds = {}); /// Thread safe execution of the loaded network Status Execute(const InputTensors& inputTensors, @@ -200,8 +204,9 @@ private: // A set of vectors to record the workload queue indexes and their corresponding Input/Output Slot indexes // which are connected to Inputs and Outputs for the network. - std::vector> m_InputWorkloadSlotPairs; - std::vector> m_OutputWorkloadSlotPairs; + std::unordered_map> m_InputWorkloadSlotPairs; + std::unordered_map> m_OutputWorkloadSlotPairs; + }; } -- cgit v1.2.1