From a2747487fbe7eb6d9f5357c6d16c32355ed6e01c Mon Sep 17 00:00:00 2001 From: Sadik Armagan Date: Tue, 9 Feb 2021 10:28:54 +0000 Subject: MLCE-347 'REDUCE_MIN, REDUCE_MAX, REDUCE_SUM Support' * Added TfLiteParser support for REDUCE_MIN and REDUCE_MAX operators * Added ACL workloads support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators * Added TfLite Delegate support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators Signed-off-by: Sadik Armagan Change-Id: I8085d59946bfd4ab78a59a61f899031ae53371a8 --- delegate/src/Reduce.hpp | 133 +++++++++++++ delegate/src/armnn_delegate.cpp | 19 ++ delegate/src/test/ReduceTest.cpp | 354 +++++++++++++++++++++++++++++++++ delegate/src/test/ReduceTestHelper.hpp | 186 +++++++++++++++++ 4 files changed, 692 insertions(+) create mode 100644 delegate/src/Reduce.hpp create mode 100644 delegate/src/test/ReduceTest.cpp create mode 100644 delegate/src/test/ReduceTestHelper.hpp (limited to 'delegate/src') diff --git a/delegate/src/Reduce.hpp b/delegate/src/Reduce.hpp new file mode 100644 index 0000000000..13a11d3e61 --- /dev/null +++ b/delegate/src/Reduce.hpp @@ -0,0 +1,133 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include +#include +#include +#include +#include + +namespace armnnDelegate +{ + +TfLiteStatus VisitReduceOperator(DelegateData& delegateData, + TfLiteContext* tfLiteContext, + TfLiteNode* tfLiteNode, + int nodeIndex, + int32_t reduceOperatorCode) +{ + TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); + TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); + + const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; + const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; + if (!IsValid(tfLiteContext, tfLiteInputTensor, reduceOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[0]]; + if (!IsValid(tfLiteContext, tfLiteOutputTensor, reduceOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + + // Get const axis value from model and set it to descriptor. + const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; + if (!IsValid(tfLiteContext, tfLiteAxisTensor, reduceOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + const armnn::TensorInfo& axisTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteAxisTensor); + auto* axisTensorData = tflite::GetTensorData(&tfLiteAxisTensor); + + std::vector axis; + // Add axis data to vector to be converter to unsigned int and assigned to descriptor axis. + if (axisTensorData != nullptr) + { + for (unsigned int i = 0; i < axisTensorInfo.GetNumElements(); ++i) + { + axis.emplace_back(axisTensorData[i]); + } + } + else + { + for (unsigned int i = 0; i < inputTensorInfo.GetNumDimensions(); ++i) + { + axis.push_back(i); + } + } + + // Convert the axis to unsigned int and remove duplicates. + unsigned int rank = inputTensorInfo.GetNumDimensions(); + std::set uniqueAxis; + std::transform(axis.begin(), + axis.end(), + std::inserter(uniqueAxis, uniqueAxis.begin()), + [rank](int i)->unsigned int{ return (i + rank) % rank; }); + + armnn::ReduceDescriptor desc; + desc.m_vAxis.assign(uniqueAxis.begin(), uniqueAxis.end()); + + auto* reducerParameters = reinterpret_cast(tfLiteNode->builtin_data); + desc.m_KeepDims = reducerParameters->keep_dims; + if (reduceOperatorCode == kTfLiteBuiltinReduceMax) + { + desc.m_ReduceOperation = armnn::ReduceOperation::Max; + } + else if (reduceOperatorCode == kTfLiteBuiltinReduceMin) + { + desc.m_ReduceOperation = armnn::ReduceOperation::Min; + } + else if (reduceOperatorCode == kTfLiteBuiltinSum) + { + desc.m_ReduceOperation = armnn::ReduceOperation::Sum; + } + else + { + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: Unsupported Reduction Operator #%d node #%d: ", + reduceOperatorCode, nodeIndex); + return kTfLiteError; + } + + bool isSupported = false; + auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) + { + FORWARD_LAYER_SUPPORT_FUNC(__func__, + tfLiteContext, + IsReduceSupported, + delegateData.m_Backends, + isSupported, + inputTensorInfo, + outInfo, + desc); + }; + + if (!delegateData.m_Network) + { + validateFunc(outputTensorInfo, isSupported); + return isSupported ? kTfLiteOk : kTfLiteError; + } + + // Add an Reduce layer + armnn::IConnectableLayer* layer = delegateData.m_Network->AddReduceLayer(desc); + ARMNN_ASSERT(layer != nullptr); + + armnn::IOutputSlot& outputSlot = layer->GetOutputSlot(0); + outputSlot.SetTensorInfo(outputTensorInfo); + + // Connect + return Connect(layer, tfLiteNode, delegateData); +} + +} // namespace armnnDelegate diff --git a/delegate/src/armnn_delegate.cpp b/delegate/src/armnn_delegate.cpp index 3ebc0cc6b5..2b07fc7098 100644 --- a/delegate/src/armnn_delegate.cpp +++ b/delegate/src/armnn_delegate.cpp @@ -25,6 +25,7 @@ #include "Pooling.hpp" #include "Quantization.hpp" #include "Redefine.hpp" +#include "Reduce.hpp" #include "Resize.hpp" #include "Round.hpp" #include "Slice.hpp" @@ -733,6 +734,18 @@ TfLiteStatus ArmnnSubgraph::VisitNode(DelegateData& delegateData, tfLiteNode, nodeIndex, kTfLiteBuiltinRank); + case kTfLiteBuiltinReduceMax: + return VisitReduceOperator(delegateData, + tfLiteContext, + tfLiteNode, + nodeIndex, + kTfLiteBuiltinReduceMax); + case kTfLiteBuiltinReduceMin: + return VisitReduceOperator(delegateData, + tfLiteContext, + tfLiteNode, + nodeIndex, + kTfLiteBuiltinReduceMin); case kTfLiteBuiltinRelu: return VisitActivationOperator(delegateData, tfLiteContext, @@ -805,6 +818,12 @@ TfLiteStatus ArmnnSubgraph::VisitNode(DelegateData& delegateData, tfLiteNode, nodeIndex, kTfLiteBuiltinStridedSlice); + case kTfLiteBuiltinSum: + return VisitReduceOperator(delegateData, + tfLiteContext, + tfLiteNode, + nodeIndex, + kTfLiteBuiltinSum); case kTfLiteBuiltinTranspose: return VisitTransposeOperator(delegateData, tfLiteContext, diff --git a/delegate/src/test/ReduceTest.cpp b/delegate/src/test/ReduceTest.cpp new file mode 100644 index 0000000000..49608b6a2c --- /dev/null +++ b/delegate/src/test/ReduceTest.cpp @@ -0,0 +1,354 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ReduceTestHelper.hpp" + +#include + +#include +#include + +#include + +namespace armnnDelegate +{ + +void ReduceUint8KeepDimsTest(tflite::BuiltinOperator reduceOperatorCode, + std::vector& backends, + std::vector& expectedOutputValues) +{ + std::vector input0Shape { 1, 1, 2, 3 }; + std::vector input1Shape { 1 }; + std::vector expectedOutputShape { 1, 1, 1, 3 }; + + std::vector input0Values { 1, 2, 3, + 4, 3, 1 }; // Inputs + std::vector input1Values { 2 }; // Axis + + ReduceTest(reduceOperatorCode, + ::tflite::TensorType_UINT8, + backends, + input0Shape, + input1Shape, + expectedOutputShape, + input0Values, + input1Values, + expectedOutputValues, + true); +} + +void ReduceUint8Test(tflite::BuiltinOperator reduceOperatorCode, + std::vector& backends, + std::vector& expectedOutputValues) +{ + std::vector input0Shape { 1, 1, 2, 3 }; + std::vector input1Shape { 1 }; + std::vector expectedOutputShape { 1, 1, 3 }; + + std::vector input0Values { 1, 2, 3, + 4, 3, 1 }; // Inputs + std::vector input1Values { 2 }; // Axis + + ReduceTest(reduceOperatorCode, + ::tflite::TensorType_UINT8, + backends, + input0Shape, + input1Shape, + expectedOutputShape, + input0Values, + input1Values, + expectedOutputValues, + false); +} + +void ReduceFp32KeepDimsTest(tflite::BuiltinOperator reduceOperatorCode, + std::vector& backends, + std::vector& expectedOutputValues) +{ + std::vector input0Shape { 1, 1, 2, 3 }; + std::vector input1Shape { 1 }; + std::vector expectedOutputShape { 1, 1, 1, 3 }; + + std::vector input0Values { 1001.0f, 11.0f, 1003.0f, + 10.0f, 1002.0f, 12.0f }; // Inputs + std::vector input1Values { 2 }; // Axis + + ReduceTest(reduceOperatorCode, + ::tflite::TensorType_FLOAT32, + backends, + input0Shape, + input1Shape, + expectedOutputShape, + input0Values, + input1Values, + expectedOutputValues, + true); +} + +void ReduceFp32Test(tflite::BuiltinOperator reduceOperatorCode, + std::vector& backends, + std::vector& expectedOutputValues) +{ + std::vector input0Shape { 1, 1, 2, 3 }; + std::vector input1Shape { 1 }; + std::vector expectedOutputShape { 1, 1, 3 }; + + std::vector input0Values { 1001.0f, 11.0f, 1003.0f, + 10.0f, 1002.0f, 12.0f }; // Inputs + std::vector input1Values { 2 }; // Axis + + ReduceTest(reduceOperatorCode, + ::tflite::TensorType_FLOAT32, + backends, + input0Shape, + input1Shape, + expectedOutputShape, + input0Values, + input1Values, + expectedOutputValues, + false); +} + +// REDUCE_MAX Tests +TEST_SUITE("ReduceMax_CpuRefTests") +{ + +TEST_CASE ("ReduceMax_Uint8_KeepDims_CpuRef_Test") +{ + std::vector backends = {armnn::Compute::CpuRef}; + std::vector expectedOutputValues { 4, 3, 3 }; + ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +TEST_CASE ("ReduceMax_Uint8_CpuRef_Test") +{ + std::vector backends = {armnn::Compute::CpuRef}; + std::vector expectedOutputValues { 4, 3, 3 }; + ReduceUint8Test(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +TEST_CASE ("ReduceMax_Fp32_KeepDims_CpuRef_Test") +{ + std::vector backends = {armnn::Compute::CpuRef}; + std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; + ReduceFp32KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +TEST_CASE ("ReduceMax_Fp32_CpuRef_Test") +{ + std::vector backends = {armnn::Compute::CpuRef}; + std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; + ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +} // End of ReduceMax_CpuRefTests + +TEST_SUITE("ReduceMax_CpuAccTests") +{ + +TEST_CASE ("ReduceMax_Uint8_KeepDims_CpuAcc_Test") +{ + std::vector backends = {armnn::Compute::CpuAcc}; + std::vector expectedOutputValues { 4, 3, 3 }; + ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +TEST_CASE ("ReduceMax_Uint8_CpuAcc_Test") +{ + std::vector backends = {armnn::Compute::CpuAcc}; + std::vector expectedOutputValues { 4, 3, 3 }; + ReduceUint8Test(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + + +TEST_CASE ("ReduceMax_Fp32_KeepDims_CpuAcc_Test") +{ + std::vector backends = {armnn::Compute::CpuAcc}; + std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; + ReduceFp32KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +TEST_CASE ("ReduceMax_Fp32_CpuAcc_Test") +{ + std::vector backends = {armnn::Compute::CpuAcc}; + std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; + ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +} // End of ReduceMax_CpuAccTests + +TEST_SUITE("ReduceMax_GpuAccTests") +{ + +TEST_CASE ("ReduceMax_Uint8_KeepDims_GpuAcc_Test") +{ + std::vector backends = {armnn::Compute::GpuAcc}; + std::vector expectedOutputValues { 4, 3, 3 }; + ReduceUint8KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +TEST_CASE ("ReduceMax_Uint8_GpuAcc_Test") +{ + std::vector backends = {armnn::Compute::GpuAcc}; + std::vector expectedOutputValues { 4, 3, 3 }; + ReduceUint8Test(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + + +TEST_CASE ("ReduceMax_Fp32_KeepDims_GpuAcc_Test") +{ + std::vector backends = {armnn::Compute::GpuAcc}; + std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; + ReduceFp32KeepDimsTest(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +TEST_CASE ("ReduceMax_Fp32_GpuAcc_Test") +{ + std::vector backends = {armnn::Compute::GpuAcc}; + std::vector expectedOutputValues { 1001.0f, 1002.0f, 1003.0f }; + ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MAX, + backends, + expectedOutputValues); +} + +} // End of ReduceMax_GpuAccTests + +// REDUCE_MIN Tests +TEST_SUITE("ReduceMin_CpuRefTests") +{ + +TEST_CASE ("ReduceMin_Fp32_CpuRef_Test") +{ + std::vector backends = {armnn::Compute::CpuRef}; + std::vector expectedOutputValues { 10.0f, 11.0f, 12.0f }; + ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MIN, + backends, + expectedOutputValues); +} + +} // End of ReduceMin_CpuRefTests + +TEST_SUITE("ReduceMin_CpuAccTests") +{ + +TEST_CASE ("ReduceMin_Fp32_CpuAcc_Test") +{ + std::vector backends = {armnn::Compute::CpuAcc}; + std::vector expectedOutputValues { 10.0f, 11.0f, 12.0f }; + ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MIN, + backends, + expectedOutputValues); +} + +} // End of ReduceMin_CpuAccTests + +TEST_SUITE("ReduceMin_GpuAccTests") +{ + +TEST_CASE ("ReduceMin_Fp32_GpuAcc_Test") +{ + std::vector backends = {armnn::Compute::GpuAcc}; + std::vector expectedOutputValues { 10.0f, 11.0f, 12.0f }; + ReduceFp32Test(tflite::BuiltinOperator_REDUCE_MIN, + backends, + expectedOutputValues); +} + +} // End of ReduceMin_GpuAccTests + +// SUM Tests +TEST_SUITE("Sum_CpuRefTests") +{ + +TEST_CASE ("Sum_Uint8_KeepDims_CpuRef_Test") +{ + std::vector backends = {armnn::Compute::CpuRef}; + std::vector expectedOutputValues { 5, 5, 4 }; + ReduceUint8KeepDimsTest(tflite::BuiltinOperator_SUM, + backends, + expectedOutputValues); +} + +TEST_CASE ("Sum_Fp32_CpuRef_Test") +{ + std::vector backends = {armnn::Compute::CpuRef}; + std::vector expectedOutputValues { 1011.0f, 1013.0f, 1015.0f }; + ReduceFp32Test(tflite::BuiltinOperator_SUM, + backends, + expectedOutputValues); +} + +} // End of Sum_CpuRefTests + +TEST_SUITE("Sum_CpuAccTests") +{ + +TEST_CASE ("Sum_Uint8_KeepDims_CpuAcc_Test") +{ + std::vector backends = {armnn::Compute::CpuAcc}; + std::vector expectedOutputValues { 5, 5, 4 }; + ReduceUint8KeepDimsTest(tflite::BuiltinOperator_SUM, + backends, + expectedOutputValues); +} + +TEST_CASE ("Sum_Fp32_CpuAcc_Test") +{ + std::vector backends = {armnn::Compute::CpuAcc}; + std::vector expectedOutputValues { 1011.0f, 1013.0f, 1015.0f }; + ReduceFp32Test(tflite::BuiltinOperator_SUM, + backends, + expectedOutputValues); +} + +} // End of Sum_CpuAccTests + +TEST_SUITE("Sum_GpuAccTests") +{ + +TEST_CASE ("Sum_Uint8_KeepDims_GpuAcc_Test") +{ + std::vector backends = {armnn::Compute::GpuAcc}; + std::vector expectedOutputValues { 5, 5, 4 }; + ReduceUint8KeepDimsTest(tflite::BuiltinOperator_SUM, + backends, + expectedOutputValues); +} + +TEST_CASE ("Sum_Fp32_GpuAcc_Test") +{ + std::vector backends = {armnn::Compute::GpuAcc}; + std::vector expectedOutputValues { 1011.0f, 1013.0f, 1015.0f }; + ReduceFp32Test(tflite::BuiltinOperator_SUM, + backends, + expectedOutputValues); +} + +} // End of Sum_GpuAccTests + + +} // namespace armnnDelegate \ No newline at end of file diff --git a/delegate/src/test/ReduceTestHelper.hpp b/delegate/src/test/ReduceTestHelper.hpp new file mode 100644 index 0000000000..b41fcfa39b --- /dev/null +++ b/delegate/src/test/ReduceTestHelper.hpp @@ -0,0 +1,186 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include "TestUtils.hpp" + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +namespace +{ + +std::vector CreateReduceTfLiteModel(tflite::BuiltinOperator reduceOperatorCode, + tflite::TensorType tensorType, + std::vector& input0TensorShape, + std::vector& input1TensorShape, + const std::vector & outputTensorShape, + std::vector& axisData, + const bool keepDims, + float quantScale = 1.0f, + int quantOffset = 0) +{ + using namespace tflite; + flatbuffers::FlatBufferBuilder flatBufferBuilder; + + std::array, 2> buffers; + buffers[0] = CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector({})); + buffers[1] = CreateBuffer(flatBufferBuilder, + flatBufferBuilder.CreateVector(reinterpret_cast(axisData.data()), + sizeof(int32_t) * axisData.size())); + + auto quantizationParameters = + CreateQuantizationParameters(flatBufferBuilder, + 0, + 0, + flatBufferBuilder.CreateVector({ quantScale }), + flatBufferBuilder.CreateVector({ quantOffset })); + + std::array, 3> tensors; + tensors[0] = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(input0TensorShape.data(), + input0TensorShape.size()), + tensorType, + 0, + flatBufferBuilder.CreateString("input"), + quantizationParameters); + + tensors[1] = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(input1TensorShape.data(), + input1TensorShape.size()), + ::tflite::TensorType_INT32, + 1, + flatBufferBuilder.CreateString("axis"), + quantizationParameters); + + // Create output tensor + tensors[2] = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(outputTensorShape.data(), + outputTensorShape.size()), + tensorType, + 0, + flatBufferBuilder.CreateString("output"), + quantizationParameters); + + // Create operator. Reduce operations MIN, MAX, SUM, MEAN uses ReducerOptions. + tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_ReducerOptions; + flatbuffers::Offset operatorBuiltinOptions = CreateReducerOptions(flatBufferBuilder, keepDims).Union(); + + const std::vector operatorInputs{ {0, 1} }; + const std::vector operatorOutputs{ 2 }; + flatbuffers::Offset reduceOperator = + CreateOperator(flatBufferBuilder, + 0, + flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), + flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), + operatorBuiltinOptionsType, + operatorBuiltinOptions); + + const std::vector subgraphInputs{ {0, 1} }; + const std::vector subgraphOutputs{ 2 }; + flatbuffers::Offset subgraph = + CreateSubGraph(flatBufferBuilder, + flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), + flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), + flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), + flatBufferBuilder.CreateVector(&reduceOperator, 1)); + + flatbuffers::Offset modelDescription = + flatBufferBuilder.CreateString("ArmnnDelegate: Reduce Operator Model"); + flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, reduceOperatorCode); + + flatbuffers::Offset flatbufferModel = + CreateModel(flatBufferBuilder, + TFLITE_SCHEMA_VERSION, + flatBufferBuilder.CreateVector(&operatorCode, 1), + flatBufferBuilder.CreateVector(&subgraph, 1), + modelDescription, + flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); + + flatBufferBuilder.Finish(flatbufferModel); + + return std::vector(flatBufferBuilder.GetBufferPointer(), + flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); +} + +template +void ReduceTest(tflite::BuiltinOperator reduceOperatorCode, + tflite::TensorType tensorType, + std::vector& backends, + std::vector& input0Shape, + std::vector& input1Shape, + std::vector& expectedOutputShape, + std::vector& input0Values, + std::vector& input1Values, + std::vector& expectedOutputValues, + const bool keepDims, + float quantScale = 1.0f, + int quantOffset = 0) +{ + using namespace tflite; + std::vector modelBuffer = CreateReduceTfLiteModel(reduceOperatorCode, + tensorType, + input0Shape, + input1Shape, + expectedOutputShape, + input1Values, + keepDims, + quantScale, + quantOffset); + + const Model* tfLiteModel = GetModel(modelBuffer.data()); + + // Create TfLite Interpreters + std::unique_ptr armnnDelegateInterpreter; + CHECK(InterpreterBuilder(tfLiteModel, ::tflite::ops::builtin::BuiltinOpResolver()) + (&armnnDelegateInterpreter) == kTfLiteOk); + CHECK(armnnDelegateInterpreter != nullptr); + CHECK(armnnDelegateInterpreter->AllocateTensors() == kTfLiteOk); + + std::unique_ptr tfLiteInterpreter; + CHECK(InterpreterBuilder(tfLiteModel, ::tflite::ops::builtin::BuiltinOpResolver()) + (&tfLiteInterpreter) == kTfLiteOk); + CHECK(tfLiteInterpreter != nullptr); + CHECK(tfLiteInterpreter->AllocateTensors() == kTfLiteOk); + + // Create the ArmNN Delegate + armnnDelegate::DelegateOptions delegateOptions(backends); + std::unique_ptr + theArmnnDelegate(armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions), + armnnDelegate::TfLiteArmnnDelegateDelete); + CHECK(theArmnnDelegate != nullptr); + + // Modify armnnDelegateInterpreter to use armnnDelegate + CHECK(armnnDelegateInterpreter->ModifyGraphWithDelegate(theArmnnDelegate.get()) == kTfLiteOk); + + // Set input data + armnnDelegate::FillInput(tfLiteInterpreter, 0, input0Values); + armnnDelegate::FillInput(armnnDelegateInterpreter, 0, input0Values); + + // Run EnqueWorkload + CHECK(tfLiteInterpreter->Invoke() == kTfLiteOk); + CHECK(armnnDelegateInterpreter->Invoke() == kTfLiteOk); + + // Compare output data + armnnDelegate::CompareOutputData(tfLiteInterpreter, + armnnDelegateInterpreter, + expectedOutputShape, + expectedOutputValues); + + armnnDelegateInterpreter.reset(nullptr); +} + +} // anonymous namespace \ No newline at end of file -- cgit v1.2.1