From bb79a175ac8c6f9a5841a323b07896fbe97700fd Mon Sep 17 00:00:00 2001 From: Sadik Armagan Date: Fri, 5 Aug 2022 16:12:49 +0100 Subject: IVGCVSW-7154 'Constant Tensors As Inputs' * Fixed the issues about converting Conv2D and DepthwiseConv2d input issues * Read 1D input tensors that do not have shape specified Signed-off-by: Sadik Armagan Change-Id: I12f3d1c57a2afedac42c6e7b31e4b1fc689abeca --- delegate/src/Activation.hpp | 4 +-- delegate/src/ArgMinMax.hpp | 4 +-- delegate/src/BatchSpace.hpp | 6 ++-- delegate/src/Comparison.hpp | 4 +-- delegate/src/Control.hpp | 6 ++-- delegate/src/Convolution.hpp | 44 ++++++++++++++++------------- delegate/src/DelegateUtils.hpp | 24 +++++++++++++--- delegate/src/ElementwiseBinary.hpp | 4 +-- delegate/src/ElementwiseUnary.hpp | 4 +-- delegate/src/Fill.hpp | 4 +-- delegate/src/FullyConnected.hpp | 4 +-- delegate/src/Gather.hpp | 2 +- delegate/src/GatherNd.hpp | 2 +- delegate/src/LogicalBinary.hpp | 4 +-- delegate/src/Lstm.hpp | 4 +-- delegate/src/Normalization.hpp | 6 ++-- delegate/src/Pack.hpp | 2 +- delegate/src/Pad.hpp | 4 +-- delegate/src/Pooling.hpp | 4 +-- delegate/src/Prelu.hpp | 4 +-- delegate/src/Quantization.hpp | 9 +++--- delegate/src/Redefine.hpp | 6 ++-- delegate/src/Reduce.hpp | 4 +-- delegate/src/Resize.hpp | 4 +-- delegate/src/Round.hpp | 4 +-- delegate/src/Shape.hpp | 4 +-- delegate/src/Slice.hpp | 2 +- delegate/src/Softmax.hpp | 4 +-- delegate/src/SpaceDepth.hpp | 6 ++-- delegate/src/Split.hpp | 4 +-- delegate/src/Transpose.hpp | 4 +-- delegate/src/UnidirectionalSequenceLstm.hpp | 4 +-- delegate/src/Unpack.hpp | 4 +-- 33 files changed, 111 insertions(+), 88 deletions(-) diff --git a/delegate/src/Activation.hpp b/delegate/src/Activation.hpp index 5ac92f8802..0071873d16 100644 --- a/delegate/src/Activation.hpp +++ b/delegate/src/Activation.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -61,7 +61,7 @@ TfLiteStatus VisitActivationOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::ActivationDescriptor activationDesc; switch(operatorCode) diff --git a/delegate/src/ArgMinMax.hpp b/delegate/src/ArgMinMax.hpp index 0b0b13d6ec..057dc8ba0a 100644 --- a/delegate/src/ArgMinMax.hpp +++ b/delegate/src/ArgMinMax.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -37,7 +37,7 @@ TfLiteStatus VisitArgMinMaxOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Get const axis value from model and set it to descriptor. const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; diff --git a/delegate/src/BatchSpace.hpp b/delegate/src/BatchSpace.hpp index 5f8d5cc317..847d6f15d2 100644 --- a/delegate/src/BatchSpace.hpp +++ b/delegate/src/BatchSpace.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -50,7 +50,7 @@ TfLiteStatus VisitBatchToSpaceNdOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& blockShapeTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBlockShapeTensor); const armnn::TensorInfo& cropsTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteCropsTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); std::vector blockShape(blockShapeTensorInfo.GetNumElements()); ::memcpy(blockShape.data(), tfLiteBlockShapeTensor.data.data, blockShapeTensorInfo.GetNumBytes()); @@ -141,7 +141,7 @@ TfLiteStatus VisitSpaceToBatchNdOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& blockShapeTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteBlockShapeTensor); const armnn::TensorInfo& padListTensorInfo = GetTensorInfoForTfLiteTensor(tfLitePadListTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); std::vector blockShape(blockShapeTensorInfo.GetNumElements()); std::memcpy(blockShape.data(), tfLiteBlockShapeTensor.data.data, blockShapeTensorInfo.GetNumBytes()); diff --git a/delegate/src/Comparison.hpp b/delegate/src/Comparison.hpp index ce12e9f7c3..8bf53c71ef 100644 --- a/delegate/src/Comparison.hpp +++ b/delegate/src/Comparison.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -59,7 +59,7 @@ TfLiteStatus VisitComparisonOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); const armnn::TensorInfo& inputTensorInfo1 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor1); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::ComparisonOperation comparisonOperation = armnn::ComparisonOperation::Equal; switch(tfLiteComparisonOperatorCode) diff --git a/delegate/src/Control.hpp b/delegate/src/Control.hpp index 7e02de1bdf..f04245bcb6 100644 --- a/delegate/src/Control.hpp +++ b/delegate/src/Control.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -115,7 +115,7 @@ TfLiteStatus VisitConcatenationOperator(DelegateData& delegateData, SetupConcatViewOrigin(inputTensorInfo, concatDescriptor, concatDimInput, viewIndex, mergeDimOrigin); } - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Check if supported bool isSupported = false; @@ -232,7 +232,7 @@ TfLiteStatus VisitMeanOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& axisTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteAxisTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* axisTensorData = tflite::GetTensorData(&tfLiteAxisTensor); diff --git a/delegate/src/Convolution.hpp b/delegate/src/Convolution.hpp index 679f4dbe39..93da4c8ce2 100644 --- a/delegate/src/Convolution.hpp +++ b/delegate/src/Convolution.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -98,7 +98,7 @@ TfLiteStatus VisitConv2dOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::TensorInfo filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); @@ -163,14 +163,17 @@ TfLiteStatus VisitConv2dOperator(DelegateData& delegateData, // Set up filter and biases armnn::IConnectableLayer* layer = delegateData.m_Network->AddConvolution2dLayer(descriptor); - auto filter = - CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[1]], - filterTensorInfo, - armnn::Optional()); + if(tflite::IsConstantTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[1]])) + { + auto filter = + CreateConstTensor(&tfLiteContext->tensors[tfLiteNode->inputs->data[1]], + filterTensorInfo, + armnn::Optional()); - armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter); - weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); - weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); + armnn::IConnectableLayer *weightsLayer = delegateData.m_Network->AddConstantLayer(filter); + weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); + weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); + } if (biasEnabled) { @@ -255,7 +258,7 @@ TfLiteStatus VisitConv3dOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::TensorInfo filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); @@ -449,7 +452,7 @@ TfLiteStatus VisitDepthwiseConv2dOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::TensorInfo filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); @@ -494,9 +497,6 @@ TfLiteStatus VisitDepthwiseConv2dOperator(DelegateData& delegateData, biasTensorInfo = armnn::TensorInfo(armnn::TensorShape({1}), GetDataType(tfLiteInputTensor)); } - // For depthwise the weights layout is the same as for tflite [1, H, W, I*M]. No permutation required. - auto filter = CreateConstTensor(&tfLiteFilterTensor, filterTensorInfo); - if (!delegateData.m_Network) { bool isSupported = false; @@ -508,16 +508,22 @@ TfLiteStatus VisitDepthwiseConv2dOperator(DelegateData& delegateData, inputTensorInfo, outputTensorInfo, descriptor, - filter.GetInfo(), + filterTensorInfo, armnn::Optional(biasTensorInfo)); return isSupported ? kTfLiteOk : kTfLiteError; } armnn::IConnectableLayer* layer = delegateData.m_Network->AddDepthwiseConvolution2dLayer(descriptor); - armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter); - weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); - weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); + if(tflite::IsConstantTensor(&tfLiteFilterTensor)) + { + // For depthwise the weights layout is the same as for tflite [1, H, W, I*M]. No permutation required. + auto filter = CreateConstTensor(&tfLiteFilterTensor, filterTensorInfo); + + armnn::IConnectableLayer* weightsLayer = delegateData.m_Network->AddConstantLayer(filter); + weightsLayer->GetOutputSlot(0).Connect(layer->GetInputSlot(1u)); + weightsLayer->GetOutputSlot(0).SetTensorInfo(filterTensorInfo); + } if (biasEnabled) { @@ -663,7 +669,7 @@ TfLiteStatus VisitTransposeConv2dOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::TensorInfo filterTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteFilterTensor); // TfLite uses NHWC tensors diff --git a/delegate/src/DelegateUtils.hpp b/delegate/src/DelegateUtils.hpp index 46b2db9d64..58d8048be3 100644 --- a/delegate/src/DelegateUtils.hpp +++ b/delegate/src/DelegateUtils.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -404,14 +404,16 @@ armnn::DataType GetDataType(const TfLiteTensor& tfLiteTensor) } } -armnn::TensorInfo GetTensorInfoForTfLiteTensor(const TfLiteTensor& tfLiteTensor) +armnn::TensorInfo GetTensorInfoForTfLiteTensor(const TfLiteTensor& tfLiteTensor, bool isOutput = false) { armnn::DataType type = GetDataType(tfLiteTensor); armnn::TensorInfo ret; auto tensorDimensionSize = tfLiteTensor.dims->size; if (tensorDimensionSize == 0) { - if(tflite::IsConstantTensor(&tfLiteTensor)) + // If input tensor does not have a shape + // assuming that it has 1D tensor + if (!isOutput) { std::vector safeShape = { 1 }; bool dimensionsSpecificity[1] = { true }; @@ -419,7 +421,10 @@ armnn::TensorInfo GetTensorInfoForTfLiteTensor(const TfLiteTensor& tfLiteTensor) safeShape.data(), dimensionsSpecificity); ret = armnn::TensorInfo(tensorShape, type); - ret.SetConstant(true); + if(tflite::IsConstantTensor(&tfLiteTensor)) + { + ret.SetConstant(true); + } } else { @@ -652,4 +657,15 @@ bool AreAllSigned32(const armnn::TensorInfo& inputInfo1, (armnn::DataType::Signed32 == outputInfo.GetDataType()); } +void UpdateConstantTensorOutputs(const armnn::TensorInfo& inputInfo, armnn::TensorInfo& outputInfo) +{ + // If input tensor info is constant and output tensor info shape is not specified + // set the output shape from input shape + if (inputInfo.IsConstant() && outputInfo.GetShape().GetDimensionality() == armnn::Dimensionality::NotSpecified) + { + outputInfo.SetShape(inputInfo.GetShape()); + } + return; +} + } // namespace anonymous diff --git a/delegate/src/ElementwiseBinary.hpp b/delegate/src/ElementwiseBinary.hpp index 434694c40a..6e81db4b4f 100644 --- a/delegate/src/ElementwiseBinary.hpp +++ b/delegate/src/ElementwiseBinary.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -246,7 +246,7 @@ TfLiteStatus VisitElementwiseBinaryOperator(DelegateData& delegateData, armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor1); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) { diff --git a/delegate/src/ElementwiseUnary.hpp b/delegate/src/ElementwiseUnary.hpp index c65ddefa22..79d7f82249 100644 --- a/delegate/src/ElementwiseUnary.hpp +++ b/delegate/src/ElementwiseUnary.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -47,7 +47,7 @@ TfLiteStatus VisitElementwiseUnaryOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::ElementwiseUnaryDescriptor descriptor(unaryOperation); bool isSupported = false; diff --git a/delegate/src/Fill.hpp b/delegate/src/Fill.hpp index 859f5fffc2..dc30e53ba9 100644 --- a/delegate/src/Fill.hpp +++ b/delegate/src/Fill.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -52,7 +52,7 @@ TfLiteStatus VisitFillOperator(DelegateData& delegateData, } armnn::TensorInfo inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::FillDescriptor descriptor; switch (tfLiteFillTensor.type) diff --git a/delegate/src/FullyConnected.hpp b/delegate/src/FullyConnected.hpp index e8c13f2053..6677ab900e 100644 --- a/delegate/src/FullyConnected.hpp +++ b/delegate/src/FullyConnected.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -54,7 +54,7 @@ TfLiteStatus VisitFullyConnectedOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); armnn::TensorInfo weightsTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteWeightsTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Fully Connected Layer accepts two dimensional weights input int32_t weightsDimension = static_cast(weightsTensorInfo.GetNumDimensions()); diff --git a/delegate/src/Gather.hpp b/delegate/src/Gather.hpp index 11f3b615ce..616de7e09e 100644 --- a/delegate/src/Gather.hpp +++ b/delegate/src/Gather.hpp @@ -47,7 +47,7 @@ TfLiteStatus VisitGatherOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& indicesTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteIndicesTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::GatherDescriptor gatherDescriptor; gatherDescriptor.m_Axis = axis; diff --git a/delegate/src/GatherNd.hpp b/delegate/src/GatherNd.hpp index b2d7a50870..1e12c5cf68 100644 --- a/delegate/src/GatherNd.hpp +++ b/delegate/src/GatherNd.hpp @@ -44,7 +44,7 @@ TfLiteStatus VisitGatherNdOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& indicesTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteIndicesTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) { diff --git a/delegate/src/LogicalBinary.hpp b/delegate/src/LogicalBinary.hpp index 2e9091b9d7..562b5d3438 100644 --- a/delegate/src/LogicalBinary.hpp +++ b/delegate/src/LogicalBinary.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -44,7 +44,7 @@ TfLiteStatus VisitLogicalBinaryOperator(DelegateData& delegateData, armnn::TensorInfo inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); armnn::TensorInfo inputTensorInfo1 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor1); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Setup descriptor and assign operation armnn::LogicalBinaryDescriptor desc; diff --git a/delegate/src/Lstm.hpp b/delegate/src/Lstm.hpp index b082db66b9..253cd2162d 100644 --- a/delegate/src/Lstm.hpp +++ b/delegate/src/Lstm.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -149,7 +149,7 @@ TfLiteStatus VisitLstmOperator(DelegateData& delegateData, || params.m_OutputLayerNormWeights != nullptr); const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); unsigned int batchSize = inputTensorInfo.GetShape()[0]; unsigned int outputSize = outputTensorInfo.GetShape()[1]; diff --git a/delegate/src/Normalization.hpp b/delegate/src/Normalization.hpp index fa1c547bd4..0933552973 100644 --- a/delegate/src/Normalization.hpp +++ b/delegate/src/Normalization.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -36,7 +36,7 @@ TfLiteStatus VisitL2NormalizationOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::L2NormalizationDescriptor descriptor; descriptor.m_DataLayout = armnn::DataLayout::NHWC; @@ -95,7 +95,7 @@ TfLiteStatus VisitLocalResponseNormalizationOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::NormalizationDescriptor descriptor; descriptor.m_DataLayout = armnn::DataLayout::NHWC; diff --git a/delegate/src/Pack.hpp b/delegate/src/Pack.hpp index 2dc266bc47..458c1744c3 100644 --- a/delegate/src/Pack.hpp +++ b/delegate/src/Pack.hpp @@ -60,7 +60,7 @@ TfLiteStatus VisitPackOperator(DelegateData& delegateData, return kTfLiteError; } - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::StackDescriptor desc; desc.m_NumInputs = static_cast(numInputs); diff --git a/delegate/src/Pad.hpp b/delegate/src/Pad.hpp index 84280797b1..daedede18d 100644 --- a/delegate/src/Pad.hpp +++ b/delegate/src/Pad.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -59,7 +59,7 @@ TfLiteStatus VisitPadOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& paddingTensorInfo = GetTensorInfoForTfLiteTensor(tfLitepaddingTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Get the padding data from the input tensor auto* paddingData = tflite::GetTensorData(&tfLitepaddingTensor); diff --git a/delegate/src/Pooling.hpp b/delegate/src/Pooling.hpp index df8c3db727..dfe90cb1f9 100644 --- a/delegate/src/Pooling.hpp +++ b/delegate/src/Pooling.hpp @@ -47,7 +47,7 @@ TfLiteStatus VisitPooling2dOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::PoolingAlgorithm poolingAlgorithm; switch(tfLitePoolingOperatorCode) @@ -145,7 +145,7 @@ TfLiteStatus VisitPooling3dOperator(DelegateData& delegateData, } // Set the input and output info const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Custom Operators are defined by the name string associated to the operator. Use this to determine // which pooling algorithm to create the armnn operator with. L2 Pooling3D is unsupported in TfLite. diff --git a/delegate/src/Prelu.hpp b/delegate/src/Prelu.hpp index aef70e8e5b..398abaf4cc 100644 --- a/delegate/src/Prelu.hpp +++ b/delegate/src/Prelu.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -69,7 +69,7 @@ TfLiteStatus VisitPreluOperator(DelegateData& delegateData, const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); const armnn::TensorInfo& alphaTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteAlphaTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) { diff --git a/delegate/src/Quantization.hpp b/delegate/src/Quantization.hpp index 26a933953a..78713759fb 100644 --- a/delegate/src/Quantization.hpp +++ b/delegate/src/Quantization.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -45,9 +45,10 @@ TfLiteStatus VisitDequantizeOperator(DelegateData& delegateData, return kTfLiteError; } - const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + armnn::TensorInfo outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); + + UpdateConstantTensorOutputs(inputTensorInfo, outputTensorInfo); bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) @@ -126,7 +127,7 @@ TfLiteStatus VisitQuantizeOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) diff --git a/delegate/src/Redefine.hpp b/delegate/src/Redefine.hpp index ce25f7f18b..cdae719373 100644 --- a/delegate/src/Redefine.hpp +++ b/delegate/src/Redefine.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -41,7 +41,7 @@ TfLiteStatus VisitCastOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) @@ -137,7 +137,7 @@ TfLiteStatus VisitReshapeOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::ReshapeDescriptor reshapeDesc; std::vector targetShape; diff --git a/delegate/src/Reduce.hpp b/delegate/src/Reduce.hpp index b8db04ccf2..79f2f52185 100644 --- a/delegate/src/Reduce.hpp +++ b/delegate/src/Reduce.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -37,7 +37,7 @@ TfLiteStatus VisitReduceOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // Get const axis value from model and set it to descriptor. const TfLiteTensor& tfLiteAxisTensor = tfLiteTensors[tfLiteNode->inputs->data[1]]; diff --git a/delegate/src/Resize.hpp b/delegate/src/Resize.hpp index 63f8e6871e..b59006cdef 100644 --- a/delegate/src/Resize.hpp +++ b/delegate/src/Resize.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -86,7 +86,7 @@ TfLiteStatus VisitResizeOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); std::string layerName("Resize"); diff --git a/delegate/src/Round.hpp b/delegate/src/Round.hpp index 016af11e21..b920bd5d2f 100644 --- a/delegate/src/Round.hpp +++ b/delegate/src/Round.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -41,7 +41,7 @@ TfLiteStatus VisitFloorOperator(DelegateData& delegateData, // NOTE: looks like the outputTensorInfo is the only thing that is required for the case // where we are adding the floor layer so maybe move the other stuff inside the // if !delegateData block for efficiency. - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); // If the m_Network is a nullptr, this signals that a prerequisite TfLite callback is required to clarify the // support for the operator diff --git a/delegate/src/Shape.hpp b/delegate/src/Shape.hpp index 51aa8f143b..284dc9fbb7 100644 --- a/delegate/src/Shape.hpp +++ b/delegate/src/Shape.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -39,7 +39,7 @@ TfLiteStatus VisitShapeOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* shapeParameters = reinterpret_cast(tfLiteNode->builtin_data); if ( shapeParameters->out_type != kTfLiteInt32 && shapeParameters->out_type != kTfLiteInt64 ) diff --git a/delegate/src/Slice.hpp b/delegate/src/Slice.hpp index 04b19cb660..6e355ae741 100644 --- a/delegate/src/Slice.hpp +++ b/delegate/src/Slice.hpp @@ -111,7 +111,7 @@ TfLiteStatus VisitSliceOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(*tfLiteInputs[0]); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); bool isSupported = false; auto validateFunc = [&](const armnn::TensorInfo& outInfo, bool& isSupported) diff --git a/delegate/src/Softmax.hpp b/delegate/src/Softmax.hpp index f2570910fb..efc1cbae16 100644 --- a/delegate/src/Softmax.hpp +++ b/delegate/src/Softmax.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -82,7 +82,7 @@ TfLiteStatus VisitSoftmaxOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); if (!delegateData.m_Network) diff --git a/delegate/src/SpaceDepth.hpp b/delegate/src/SpaceDepth.hpp index ac162fbf54..593d0e7f87 100644 --- a/delegate/src/SpaceDepth.hpp +++ b/delegate/src/SpaceDepth.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -36,7 +36,7 @@ TfLiteStatus VisitSpaceToDepthOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::SpaceToDepthDescriptor descriptor; auto* params = reinterpret_cast(tfLiteNode->builtin_data); @@ -95,7 +95,7 @@ TfLiteStatus VisitDepthToSpaceOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); armnn::DepthToSpaceDescriptor descriptor; auto* params = reinterpret_cast(tfLiteNode->builtin_data); diff --git a/delegate/src/Split.hpp b/delegate/src/Split.hpp index 66e229562a..a535585699 100644 --- a/delegate/src/Split.hpp +++ b/delegate/src/Split.hpp @@ -70,7 +70,7 @@ TfLiteStatus VisitSplitOperator(DelegateData& delegateData, { return kTfLiteError; } - outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor)); + outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); @@ -224,7 +224,7 @@ TfLiteStatus VisitSplitVOperator(DelegateData& delegateData, { return kTfLiteError; } - outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor)); + outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); diff --git a/delegate/src/Transpose.hpp b/delegate/src/Transpose.hpp index 0741ad285f..80bb12254e 100644 --- a/delegate/src/Transpose.hpp +++ b/delegate/src/Transpose.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -58,7 +58,7 @@ TfLiteStatus VisitTransposeOperator(DelegateData& delegateData, } const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteTensor(tfLiteInputTensor0); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); auto* permTensorDataPtr = tflite::GetTensorData(&tfLiteInputTensor1); unsigned int numEl = tfLiteInputTensor1.dims->data[0]; diff --git a/delegate/src/UnidirectionalSequenceLstm.hpp b/delegate/src/UnidirectionalSequenceLstm.hpp index 1a02a0c1bc..64ed778231 100644 --- a/delegate/src/UnidirectionalSequenceLstm.hpp +++ b/delegate/src/UnidirectionalSequenceLstm.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -182,7 +182,7 @@ TfLiteStatus VisitUnidirectionalSequenceLstmOperator(DelegateData& delegateData, desc.m_HiddenStateZeroPoint = hiddentensorInfo.GetQuantizationOffset(); } const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); - const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true); unsigned int batchSize = inputTensorInfo.GetShape()[0]; unsigned int outputSize = outputTensorInfo.GetShape()[2]; diff --git a/delegate/src/Unpack.hpp b/delegate/src/Unpack.hpp index 447a4da9ab..aaea00532f 100644 --- a/delegate/src/Unpack.hpp +++ b/delegate/src/Unpack.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -114,7 +114,7 @@ TfLiteStatus VisitUnpackOperator(DelegateData& delegateData, { return kTfLiteError; } - outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor)); + outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor, true)); } const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); -- cgit v1.2.1