From 91a53eab529d88f78572b1155bfd07eb5de141f4 Mon Sep 17 00:00:00 2001 From: Teresa Charlin Date: Mon, 25 Apr 2022 15:47:29 +0100 Subject: IVGCVSW-6857 Add GATHERNd Support to the TfLiteParser Signed-off-by: Teresa Charlin Change-Id: I8142072f104b23c6eaf80b54cf6ddfa0393c4921 --- CMakeLists.txt | 1 + docs/05_01_parsers.dox | 1 + src/armnnTfLiteParser/TfLiteParser.cpp | 26 +++++++ src/armnnTfLiteParser/TfLiteParser.hpp | 1 + src/armnnTfLiteParser/test/GatherNd.cpp | 121 ++++++++++++++++++++++++++++++++ 5 files changed, 150 insertions(+) create mode 100644 src/armnnTfLiteParser/test/GatherNd.cpp diff --git a/CMakeLists.txt b/CMakeLists.txt index 267ad37ce8..e67c389f3d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -631,6 +631,7 @@ if(BUILD_UNIT_TESTS) src/armnnTfLiteParser/test/FloorDiv.cpp src/armnnTfLiteParser/test/FullyConnected.cpp src/armnnTfLiteParser/test/Gather.cpp + src/armnnTfLiteParser/test/GatherNd.cpp src/armnnTfLiteParser/test/L2Normalization.cpp src/armnnTfLiteParser/test/LeakyRelu.cpp src/armnnTfLiteParser/test/LoadScopeDynamicTensor.cpp diff --git a/docs/05_01_parsers.dox b/docs/05_01_parsers.dox index 7284810d42..03f2cba8d4 100644 --- a/docs/05_01_parsers.dox +++ b/docs/05_01_parsers.dox @@ -137,6 +137,7 @@ The Arm NN SDK TensorFlow Lite parser currently supports the following operators - FLOOR_DIV - FULLY_CONNECTED, Supported Fused Activation: RELU , RELU6 , TANH, NONE - GATHER +- GATHER_ND - GREATER - GREATER_EQUAL - HARD_SWISH diff --git a/src/armnnTfLiteParser/TfLiteParser.cpp b/src/armnnTfLiteParser/TfLiteParser.cpp index 44dcacc3db..32b7c63fbb 100644 --- a/src/armnnTfLiteParser/TfLiteParser.cpp +++ b/src/armnnTfLiteParser/TfLiteParser.cpp @@ -696,6 +696,7 @@ TfLiteParserImpl::TfLiteParserImpl(const OptionalAddGatherNdLayer(layerName.c_str()); + ARMNN_ASSERT(layer != nullptr); + layer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); + + auto inputTensorIndexes = AsUnsignedVector(GetInputTensorIds(m_Model, subgraphIndex, operatorIndex)); + RegisterInputSlots(subgraphIndex, operatorIndex, layer, {inputTensorIndexes[0], inputTensorIndexes[1]}); + + auto outputTensorIndexes = AsUnsignedVector(GetOutputTensorIds(m_Model, subgraphIndex, operatorIndex)); + RegisterOutputSlots(subgraphIndex, operatorIndex, layer, {outputTensorIndexes[0]}); +} + void TfLiteParserImpl::ParseDepthToSpace(size_t subgraphIndex, size_t operatorIndex) { CHECK_MODEL(m_Model, subgraphIndex, operatorIndex); diff --git a/src/armnnTfLiteParser/TfLiteParser.hpp b/src/armnnTfLiteParser/TfLiteParser.hpp index 8c9674a5a6..6a8992fc0f 100644 --- a/src/armnnTfLiteParser/TfLiteParser.hpp +++ b/src/armnnTfLiteParser/TfLiteParser.hpp @@ -136,6 +136,7 @@ private: void ParseFloorDiv(size_t subgraphIndex, size_t operatorIndex); void ParseFullyConnected(size_t subgraphIndex, size_t operatorIndex); void ParseGather(size_t subgraphIndex, size_t operatorIndex); + void ParseGatherNd(size_t subgraphIndex, size_t operatorIndex); void ParseGreater(size_t subgraphIndex, size_t operatorIndex); void ParseGreaterOrEqual(size_t subgraphIndex, size_t operatorIndex); void ParseHardSwish(size_t subgraphIndex, size_t operatorIndex); diff --git a/src/armnnTfLiteParser/test/GatherNd.cpp b/src/armnnTfLiteParser/test/GatherNd.cpp new file mode 100644 index 0000000000..899a71f881 --- /dev/null +++ b/src/armnnTfLiteParser/test/GatherNd.cpp @@ -0,0 +1,121 @@ +// +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ParserFlatbuffersFixture.hpp" + + +TEST_SUITE("TensorflowLiteParser_GatherNd") +{ +struct GatherNdFixture : public ParserFlatbuffersFixture +{ + explicit GatherNdFixture(const std::string& paramsShape, + const std::string& indicesShape, + const std::string& outputShape, + const std::string& dataType = "FLOAT32", + const std::string& scale = "1.0", + const std::string& offset = "0") + { + m_JsonString = R"( + { + "version": 3, + "operator_codes": [ { "builtin_code": "GATHER_ND" } ], + "subgraphs": [ { + "tensors": [ + { + "shape": )" + paramsShape + R"(, + "type": )" + dataType + R"(, + "buffer": 0, + "name": "params", + "quantization": { + "min": [ 0.0 ], + "max": [ 255.0 ], + "scale": [ )" + scale + R"( ], + "zero_point": [ )" + offset + R"( ], + "details_type": "NONE", + "quantized_dimension": 0 + }, + "is_variable": false, + "shape_signature": )" + paramsShape + R"( + }, + { + "shape": )" + indicesShape + R"( , + "type": "INT32", + "buffer": 1, + "name": "indices", + "quantization": { + "details_type": "NONE", + "quantized_dimension": 0 + }, + "is_variable": false + }, + { + "shape": )" + outputShape + R"(, + "type": )" + dataType + R"(, + "buffer": 2, + "name": "output", + "quantization": { + "min": [ 0.0 ], + "max": [ 255.0 ], + "scale": [ )" + scale + R"( ], + "zero_point": [ )" + offset + R"( ], + "details_type": "NONE", + "quantized_dimension": 0 + }, + "is_variable": false, + "shape_signature": )" + outputShape + R"( + } + ], + "inputs": [ 0, 1 ], + "outputs": [ 2 ], + "operators": [ + { + "opcode_index": 0, + "inputs": [ 0, 1 ], + "outputs": [ 2 ], + "builtin_options_type": "NONE", + "custom_options_format": "FLEXBUFFERS" + } + ], + } ], + "buffers" : [ + { }, + { }, + { }, + ] + } + )"; + Setup(); + } +}; + +struct SimpleGatherNdFixture : public GatherNdFixture +{ + SimpleGatherNdFixture() : GatherNdFixture("[ 5, 2 ]", "[ 3, 1 ]", "[ 3, 2 ]" ) {} +}; + +TEST_CASE_FIXTURE(SimpleGatherNdFixture, "ParseGatherNd") +{ + RunTest<2, armnn::DataType::Float32, armnn::DataType::Signed32, armnn::DataType::Float32> + (0, + {{ "params", { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 }}}, + {{ "indices", { 1, 3, 4 }}}, + {{ "output", { 3, 4, 7, 8, 9, 10 }}}); +} + +struct GatherNdUint8Fixture : public GatherNdFixture +{ + GatherNdUint8Fixture() : GatherNdFixture("[ 8 ]", "[ 3, 1 ]", "[ 3 ]", "UINT8") {} +}; + +TEST_CASE_FIXTURE(GatherNdUint8Fixture, "ParseGatherNdUint8") +{ + RunTest<1, armnn::DataType::QAsymmU8, armnn::DataType::Signed32, armnn::DataType::QAsymmU8> + (0, + {{ "params", { 1, 2, 3, 4, 5, 6, 7, 8 }}}, + {{ "indices", { 7, 6, 5 }}}, + {{ "output", { 8, 7, 6 }}}); +} + +} -- cgit v1.2.1