From 39954b04bc8ea7ad72f83e95cc5c98e1c32c85cd Mon Sep 17 00:00:00 2001 From: Kevin May Date: Fri, 7 May 2021 09:32:51 +0100 Subject: IVGCVSW-5970 TfLiteDelegate: Add UNPACK operator Support Signed-off-by: Kevin May Change-Id: I23731718236043b46c143eaf416cb375edd93983 --- delegate/CMakeLists.txt | 5 +- delegate/src/Unpack.hpp | 184 ++++++++++++++++++++++++++++++++ delegate/src/armnn_delegate.cpp | 7 ++ delegate/src/test/UnpackTest.cpp | 179 +++++++++++++++++++++++++++++++ delegate/src/test/UnpackTestHelper.hpp | 185 +++++++++++++++++++++++++++++++++ 5 files changed, 559 insertions(+), 1 deletion(-) create mode 100644 delegate/src/Unpack.hpp create mode 100644 delegate/src/test/UnpackTest.cpp create mode 100644 delegate/src/test/UnpackTestHelper.hpp diff --git a/delegate/CMakeLists.txt b/delegate/CMakeLists.txt index dc65a1942e..84c4158b5f 100644 --- a/delegate/CMakeLists.txt +++ b/delegate/CMakeLists.txt @@ -45,6 +45,7 @@ list(APPEND armnnDelegate_sources src/Softmax.hpp src/SpaceDepth.hpp src/Split.hpp + src/Unpack.hpp src/Transpose.hpp) add_library(armnnDelegate SHARED ${armnnDelegate_sources}) @@ -173,7 +174,9 @@ if(BUILD_UNIT_TESTS) src/test/TestUtils.hpp src/test/TestUtils.cpp src/test/TransposeTest.cpp - src/test/TransposeTestHelper.hpp) + src/test/TransposeTestHelper.hpp + src/test/UnpackTest.cpp + src/test/UnpackTestHelper.hpp) # There's a known Android NDK bug which causes a subset of NeonLayerTests to # fail. We'll exclude these tests in NeonLayerTests_NDK_Bug.cpp if we're doing diff --git a/delegate/src/Unpack.hpp b/delegate/src/Unpack.hpp new file mode 100644 index 0000000000..87200ff431 --- /dev/null +++ b/delegate/src/Unpack.hpp @@ -0,0 +1,184 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include + +#include "DelegateUtils.hpp" + +#include +#include +#include +#include +#include + +namespace armnnDelegate +{ + +TfLiteStatus VisitUnpackOperator(DelegateData& delegateData, + TfLiteContext* tfLiteContext, + TfLiteNode* tfLiteNode, + int nodeIndex, + int32_t operatorCode) +{ + TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); + + const TfLiteTensor* tfLiteTensors = tfLiteContext->tensors; + const TfLiteTensor& tfLiteInputTensor = tfLiteTensors[tfLiteNode->inputs->data[0]]; + + if (!IsValid(tfLiteContext, tfLiteInputTensor, operatorCode, nodeIndex)) + { + return kTfLiteError; + } + + // Get Unpack Axis + const auto params = reinterpret_cast(tfLiteNode->builtin_data); + + const unsigned int unpackAxis = NonNegative(params->axis, nodeIndex); + + const armnn::TensorInfo& inputTensorInfo = GetTensorInfoForTfLiteTensor(tfLiteInputTensor); + + if (unpackAxis >= inputTensorInfo.GetNumDimensions()) + { + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: The unpack axis #%d cannot be greater than or equal to " + "the number of input dimensions #%d in operator #%d node #%d", + unpackAxis, inputTensorInfo.GetNumDimensions(), operatorCode, nodeIndex); + return kTfLiteError; + } + + // Get Unpack Num + unsigned int unpackNum = NonNegative(params->num, nodeIndex); + + // If num is not defined, automatically infer from the length of the dimension axis. + if(unpackNum == 0) + { + unpackNum = inputTensorInfo.GetShape()[unpackAxis]; + } + + // If unpack number cannot be inferred and is still zero, return kTfLiteError. + if(unpackNum == 0) + { + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: Number to unpack must greater than zero in operator #%d node #%d: ", + operatorCode, nodeIndex); + return kTfLiteError; + } + + // Check outputs + TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, unpackNum, nodeIndex)); + + + auto inputDimSize = inputTensorInfo.GetNumDimensions(); + std::vector unpackDimSizes(inputDimSize); + + // Add current input shape to unpackDimSizes + for (unsigned int i = 0; i < inputDimSize; ++i) + { + unpackDimSizes[i] = inputTensorInfo.GetShape()[i]; + } + + if (unpackDimSizes[unpackAxis] != unpackNum) + { + TF_LITE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnDelegate: Number to unpack must be the same as length " + "of the dimension to unpack along in operator #%d node #%d: ", + operatorCode, nodeIndex); + return kTfLiteError; + } + + unpackDimSizes[unpackAxis] /= unpackNum; + + armnn::SplitterDescriptor splitDesc(unpackNum, static_cast(unpackDimSizes.size())); + for (unsigned int j = 0; j < unpackNum; ++j) + { + // Set the size of the views. + for (unsigned int dimIdx = 0; dimIdx < unpackDimSizes.size(); ++dimIdx) + { + splitDesc.SetViewSize(j, dimIdx, unpackDimSizes[dimIdx]); + } + splitDesc.SetViewOriginCoord(j, unpackAxis, unpackDimSizes[unpackAxis] * j); + } + + std::vector outputs; + for (unsigned int i = 0; i < unpackNum; ++i) + { + const TfLiteTensor& tfLiteOutputTensor = tfLiteTensors[tfLiteNode->outputs->data[i]]; + if (!IsValid(tfLiteContext, tfLiteOutputTensor, operatorCode, nodeIndex)) + { + return kTfLiteError; + } + outputs.push_back(GetTensorInfoForTfLiteTensor(tfLiteOutputTensor)); + } + const std::vector> outputTensorInfos(outputs.begin(), outputs.end()); + + if (!delegateData.m_Network) + { + // Check if supported + bool isSupported = false; + FORWARD_LAYER_SUPPORT_FUNC(__func__, + tfLiteContext, + IsSplitterSupported, + delegateData.m_Backends, + isSupported, + inputTensorInfo, + outputTensorInfos, + splitDesc); + return isSupported ? kTfLiteOk : kTfLiteError; + } + + std::string splitterLayerName("Unpack Splitter"); + + armnn::IConnectableLayer* splitterLayer = delegateData.m_Network->AddSplitterLayer(splitDesc, + splitterLayerName.c_str()); + ARMNN_ASSERT(splitterLayer != nullptr); + + for (unsigned int k = 0; k < splitterLayer->GetNumOutputSlots(); ++k) + { + splitterLayer->GetOutputSlot(k).SetTensorInfo(outputs[k]); + } + + // Connect the input slots + delegateData.m_OutputSlotForNode[tfLiteNode->inputs->data[0]]->Connect(splitterLayer->GetInputSlot(0)); + + armnn::TensorShape splitOutShape = armnn::TensorShape(static_cast(unpackDimSizes.size()), + unpackDimSizes.data()); + + // Create reshape to remove the unpacked dimension for unpack operator of each output from Splitter. + for (unsigned int outputIndex = 0; outputIndex < splitterLayer->GetNumOutputSlots(); ++outputIndex) + { + armnn::TensorInfo outputTensorInfo = outputTensorInfos[outputIndex]; + + std::string reshapeLayerName("Unpack Reshape"); + armnn::ReshapeDescriptor reshapeDescriptor; + reshapeDescriptor.m_TargetShape = outputTensorInfo.GetShape(); + armnn::IConnectableLayer* reshapeLayer = delegateData.m_Network->AddReshapeLayer(reshapeDescriptor, + reshapeLayerName.c_str()); + + ARMNN_ASSERT(reshapeLayer != nullptr); + + splitterLayer->GetOutputSlot(outputIndex).SetTensorInfo(armnn::TensorInfo(splitOutShape, + outputTensorInfo.GetDataType(), + outputTensorInfo.GetQuantizationScale(), + outputTensorInfo.GetQuantizationOffset())); + splitterLayer->GetOutputSlot(outputIndex).Connect(reshapeLayer->GetInputSlot(0)); + + reshapeLayer->GetOutputSlot(0).SetTensorInfo(outputTensorInfo); + + armnn::IOutputSlot& slot = reshapeLayer->GetOutputSlot(0); + + delegateData.m_OutputSlotForNode[ + static_cast(tfLiteNode->outputs->data[outputIndex])] = &slot; + + } + + return kTfLiteOk; +} + +} // namespace armnnDelegate diff --git a/delegate/src/armnn_delegate.cpp b/delegate/src/armnn_delegate.cpp index d777eff27c..7e4f5b5602 100644 --- a/delegate/src/armnn_delegate.cpp +++ b/delegate/src/armnn_delegate.cpp @@ -34,6 +34,7 @@ #include "SpaceDepth.hpp" #include "Split.hpp" #include "Transpose.hpp" +#include "Unpack.hpp" #include #include @@ -881,6 +882,12 @@ TfLiteStatus ArmnnSubgraph::VisitNode(DelegateData& delegateData, tfLiteNode, nodeIndex, kTfLiteBuiltinTanh); + case kTfLiteBuiltinUnpack: + return VisitUnpackOperator(delegateData, + tfLiteContext, + tfLiteNode, + nodeIndex, + kTfLiteBuiltinUnpack); default: return kTfLiteError; } diff --git a/delegate/src/test/UnpackTest.cpp b/delegate/src/test/UnpackTest.cpp new file mode 100644 index 0000000000..c036f649ef --- /dev/null +++ b/delegate/src/test/UnpackTest.cpp @@ -0,0 +1,179 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "UnpackTestHelper.hpp" + +#include + +#include +#include + +#include + +namespace armnnDelegate +{ + +template +void UnpackAxis0Num4Test(tflite::TensorType tensorType, std::vector& backends) +{ + std::vector inputShape { 4, 1, 6 }; + std::vector expectedOutputShape { 1, 6 }; + + std::vector inputValues { 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24 }; + + std::vector expectedOutputValues0 { 1, 2, 3, 4, 5, 6 }; + std::vector expectedOutputValues1 { 7, 8, 9, 10, 11, 12 }; + std::vector expectedOutputValues2 { 13, 14, 15, 16, 17, 18 }; + std::vector expectedOutputValues3 { 19, 20, 21, 22, 23, 24 }; + + std::vector> expectedOutputValues{ expectedOutputValues0, + expectedOutputValues1, + expectedOutputValues2, + expectedOutputValues3 }; + + UnpackTest(tflite::BuiltinOperator_UNPACK, + tensorType, + backends, + inputShape, + expectedOutputShape, + inputValues, + expectedOutputValues, + 0); +} + +template +void UnpackAxis2Num6Test(tflite::TensorType tensorType, std::vector& backends) +{ + std::vector inputShape { 4, 1, 6 }; + std::vector expectedOutputShape { 4, 1 }; + + std::vector inputValues { 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, + 19, 20, 21, 22, 23, 24 }; + + std::vector expectedOutputValues0 { 1, 7, 13, 19 }; + std::vector expectedOutputValues1 { 2, 8, 14, 20 }; + std::vector expectedOutputValues2 { 3, 9, 15, 21 }; + std::vector expectedOutputValues3 { 4, 10, 16, 22 }; + std::vector expectedOutputValues4 { 5, 11, 17, 23 }; + std::vector expectedOutputValues5 { 6, 12, 18, 24 }; + + std::vector> expectedOutputValues{ expectedOutputValues0, + expectedOutputValues1, + expectedOutputValues2, + expectedOutputValues3, + expectedOutputValues4, + expectedOutputValues5 }; + + UnpackTest(tflite::BuiltinOperator_UNPACK, + tensorType, + backends, + inputShape, + expectedOutputShape, + inputValues, + expectedOutputValues, + 2); +} + +TEST_SUITE("Unpack_CpuRefTests") +{ + +// Fp32 +TEST_CASE ("Unpack_Fp32_Axis0_Num4_CpuRef_Test") +{ +std::vector backends = {armnn::Compute::CpuRef}; +UnpackAxis0Num4Test(tflite::TensorType_FLOAT32, backends); +} + +TEST_CASE ("Unpack_Fp32_Axis2_Num6_CpuRef_Test") +{ +std::vector backends = {armnn::Compute::CpuRef}; +UnpackAxis2Num6Test(tflite::TensorType_FLOAT32, backends); +} + +// Uint8 +TEST_CASE ("Unpack_Uint8_Axis0_Num4_CpuRef_Test") +{ +std::vector backends = {armnn::Compute::CpuRef}; +UnpackAxis0Num4Test(tflite::TensorType_UINT8, backends); +} + +TEST_CASE ("Unpack_Uint8_Axis2_Num6_CpuRef_Test") +{ +std::vector backends = {armnn::Compute::CpuRef}; +UnpackAxis2Num6Test(tflite::TensorType_UINT8, backends); +} + +} // End of Unpack_CpuRefTests + +TEST_SUITE("Unpack_CpuAccTests") +{ + +// Fp32 +TEST_CASE ("Unpack_Fp32_Axis0_Num4_CpuAcc_Test") +{ +std::vector backends = {armnn::Compute::CpuAcc}; +UnpackAxis0Num4Test(tflite::TensorType_FLOAT32, backends); +} + +TEST_CASE ("Unpack_Fp32_Axis2_Num6_CpuAcc_Test") +{ +std::vector backends = {armnn::Compute::CpuAcc}; +UnpackAxis2Num6Test(tflite::TensorType_FLOAT32, backends); +} + +// Uint8 +TEST_CASE ("Unpack_Uint8_Axis0_Num4_CpuAcc_Test") +{ +std::vector backends = {armnn::Compute::CpuAcc}; +UnpackAxis0Num4Test(tflite::TensorType_UINT8, backends); +} + +TEST_CASE ("Unpack_Uint8_Axis2_Num6_CpuAcc_Test") +{ +std::vector backends = {armnn::Compute::CpuAcc}; +UnpackAxis2Num6Test(tflite::TensorType_UINT8, backends); +} + +} // End of Unpack_CpuAccTests + +TEST_SUITE("Unpack_GpuAccTests") +{ + +// Fp32 +TEST_CASE ("Unpack_Fp32_Axis0_Num4_GpuAcc_Test") +{ +std::vector backends = {armnn::Compute::GpuAcc}; +UnpackAxis0Num4Test(tflite::TensorType_FLOAT32, backends); +} + +TEST_CASE ("Unpack_Fp32_Axis2_Num6_GpuAcc_Test") +{ +std::vector backends = {armnn::Compute::GpuAcc}; +UnpackAxis2Num6Test(tflite::TensorType_FLOAT32, backends); +} + +// Uint8 +TEST_CASE ("Unpack_Uint8_Axis0_Num4_GpuAcc_Test") +{ +std::vector backends = {armnn::Compute::GpuAcc}; +UnpackAxis0Num4Test(tflite::TensorType_UINT8, backends); +} + +TEST_CASE ("Unpack_Uint8_Axis2_Num6_GpuAcc_Test") +{ +std::vector backends = {armnn::Compute::GpuAcc}; +UnpackAxis2Num6Test(tflite::TensorType_UINT8, backends); +} + +} // End of Unpack_GpuAccTests + +// End of Unpack Test Suite + +} // namespace armnnDelegate \ No newline at end of file diff --git a/delegate/src/test/UnpackTestHelper.hpp b/delegate/src/test/UnpackTestHelper.hpp new file mode 100644 index 0000000000..848713498f --- /dev/null +++ b/delegate/src/test/UnpackTestHelper.hpp @@ -0,0 +1,185 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include "TestUtils.hpp" + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +namespace +{ + +std::vector CreateUnpackTfLiteModel(tflite::BuiltinOperator unpackOperatorCode, + tflite::TensorType tensorType, + std::vector& inputTensorShape, + const std::vector & outputTensorShape, + const int32_t outputTensorNum, + unsigned int axis = 0, + float quantScale = 1.0f, + int quantOffset = 0) +{ + using namespace tflite; + flatbuffers::FlatBufferBuilder flatBufferBuilder; + + std::vector> buffers; + buffers.push_back(CreateBuffer(flatBufferBuilder, flatBufferBuilder.CreateVector({}))); + + auto quantizationParameters = + CreateQuantizationParameters(flatBufferBuilder, + 0, + 0, + flatBufferBuilder.CreateVector({ quantScale }), + flatBufferBuilder.CreateVector({ quantOffset })); + + const std::vector operatorInputs{ 0 }; + std::vector operatorOutputs{}; + const std::vector subgraphInputs{ 0 }; + std::vector subgraphOutputs{}; + + std::vector> tensors(outputTensorNum + 1); + + // Create input tensor + tensors[0] = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(inputTensorShape.data(), + inputTensorShape.size()), + tensorType, + 0, + flatBufferBuilder.CreateString("input"), + quantizationParameters); + + for (int i = 0; i < outputTensorNum; ++i) + { + tensors[i + 1] = CreateTensor(flatBufferBuilder, + flatBufferBuilder.CreateVector(outputTensorShape.data(), + outputTensorShape.size()), + tensorType, + 0, + flatBufferBuilder.CreateString("output" + std::to_string(i)), + quantizationParameters); + + operatorOutputs.push_back(i + 1); + subgraphOutputs.push_back(i + 1); + } + + // create operator + tflite::BuiltinOptions operatorBuiltinOptionsType = tflite::BuiltinOptions_UnpackOptions; + flatbuffers::Offset operatorBuiltinOptions = + CreateUnpackOptions(flatBufferBuilder, outputTensorNum, axis).Union(); + + flatbuffers::Offset unpackOperator = + CreateOperator(flatBufferBuilder, + 0, + flatBufferBuilder.CreateVector(operatorInputs.data(), operatorInputs.size()), + flatBufferBuilder.CreateVector(operatorOutputs.data(), operatorOutputs.size()), + operatorBuiltinOptionsType, + operatorBuiltinOptions); + + flatbuffers::Offset subgraph = + CreateSubGraph(flatBufferBuilder, + flatBufferBuilder.CreateVector(tensors.data(), tensors.size()), + flatBufferBuilder.CreateVector(subgraphInputs.data(), subgraphInputs.size()), + flatBufferBuilder.CreateVector(subgraphOutputs.data(), subgraphOutputs.size()), + flatBufferBuilder.CreateVector(&unpackOperator, 1)); + + flatbuffers::Offset modelDescription = + flatBufferBuilder.CreateString("ArmnnDelegate: Unpack Operator Model"); + flatbuffers::Offset operatorCode = CreateOperatorCode(flatBufferBuilder, unpackOperatorCode); + + flatbuffers::Offset flatbufferModel = + CreateModel(flatBufferBuilder, + TFLITE_SCHEMA_VERSION, + flatBufferBuilder.CreateVector(&operatorCode, 1), + flatBufferBuilder.CreateVector(&subgraph, 1), + modelDescription, + flatBufferBuilder.CreateVector(buffers.data(), buffers.size())); + + flatBufferBuilder.Finish(flatbufferModel); + + return std::vector(flatBufferBuilder.GetBufferPointer(), + flatBufferBuilder.GetBufferPointer() + flatBufferBuilder.GetSize()); +} + +template +void UnpackTest(tflite::BuiltinOperator unpackOperatorCode, + tflite::TensorType tensorType, + std::vector& backends, + std::vector& inputShape, + std::vector& expectedOutputShape, + std::vector& inputValues, + std::vector>& expectedOutputValues, + unsigned int axis = 0, + float quantScale = 1.0f, + int quantOffset = 0) +{ + using namespace tflite; + std::vector modelBuffer = CreateUnpackTfLiteModel(unpackOperatorCode, + tensorType, + inputShape, + expectedOutputShape, + expectedOutputValues.size(), + axis, + quantScale, + quantOffset); + + const Model* tfLiteModel = GetModel(modelBuffer.data()); + + // Create TfLite Interpreters + std::unique_ptr armnnDelegateInterpreter; + CHECK(InterpreterBuilder(tfLiteModel, ::tflite::ops::builtin::BuiltinOpResolver()) + (&armnnDelegateInterpreter) == kTfLiteOk); + CHECK(armnnDelegateInterpreter != nullptr); + CHECK(armnnDelegateInterpreter->AllocateTensors() == kTfLiteOk); + + std::unique_ptr tfLiteInterpreter; + CHECK(InterpreterBuilder(tfLiteModel, ::tflite::ops::builtin::BuiltinOpResolver()) + (&tfLiteInterpreter) == kTfLiteOk); + CHECK(tfLiteInterpreter != nullptr); + CHECK(tfLiteInterpreter->AllocateTensors() == kTfLiteOk); + + // Create the ArmNN Delegate + armnnDelegate::DelegateOptions delegateOptions(backends); + std::unique_ptr + theArmnnDelegate(armnnDelegate::TfLiteArmnnDelegateCreate(delegateOptions), + armnnDelegate::TfLiteArmnnDelegateDelete); + CHECK(theArmnnDelegate != nullptr); + + // Modify armnnDelegateInterpreter to use armnnDelegate + CHECK(armnnDelegateInterpreter->ModifyGraphWithDelegate(theArmnnDelegate.get()) == kTfLiteOk); + + // Set input data + armnnDelegate::FillInput(tfLiteInterpreter, 0, inputValues); + armnnDelegate::FillInput(armnnDelegateInterpreter, 0, inputValues); + + + // Run EnqueueWorkload + CHECK(tfLiteInterpreter->Invoke() == kTfLiteOk); + CHECK(armnnDelegateInterpreter->Invoke() == kTfLiteOk); + + // Compare output data + for (unsigned int i = 0; i < expectedOutputValues.size(); ++i) + { + armnnDelegate::CompareOutputData(tfLiteInterpreter, + armnnDelegateInterpreter, + expectedOutputShape, + expectedOutputValues[i], + i); + } + + armnnDelegateInterpreter.reset(nullptr); +} + +} // anonymous namespace \ No newline at end of file -- cgit v1.2.1