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2023-01-25Fix incorrect copyright noticesMatthew Sloyan
* Updated headers that were missing a copyright notice. * Reverted years that were incorrectly updated. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I65842f1e9b9fd5654563edd5090133cb3c89fecc
2023-01-13IVGCVSW-7173 Add Rsqrt to Tosa Ref BackendDavid Monahan
* Added ElementwiseUnary support with a mapping for Rsqrt * Added unittests * Added Rsqrt EndtoEnd tests for all backends * Changed TosaRefLayerSupport to default to false on unsupported layers Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I3eaa9c684647ead61520a563815581aa68bee51b
2023-01-12IVGCVSW-5128 Add EndToEnd test for REDUCE_SUMTeresa Charlin
* Call Reshape EndToEnd test from 3 backends * Tidy up some naming of tests. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I5546af35e89d352d3f1529368518aecc0a4a534b
2022-12-15Change the semantics of RefTensorHandle::Import to 'overlay' existing memoryMatthew Bentham
This makes it possible to call Import on an Allocated() or memory-managed Tensor, which is needed for the current implementation of OptimizerOptions::m_ExportEnabled to work (as the last layer before the OutputLayer needs to be able to Import the user's OutputTensor, but this is done after other memory allocation). Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: I1a885c2da7b1f0f3964ae53b8135b5e96a66614f
2022-12-14Refactor: Remove m_ImportFlags from RefTensorHandleMatthew Bentham
The import flags for a RefTensorHandle shouldn't be a data member, as RefTensorHandle can only import from MemorySource::Malloc. Instead, use m_ImportEnabled to determine what to return from GetImportFlags(). Simplifies the code in Import and CanBeImported. Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: Ic629858920f7dd32f99ee27f150b81d8b67144cf
2022-12-12Updates following execution of Includewhatyouuse on armnn/include.Colm Donelan
This tool forces explicit includes of all dependencies and highlights unused dependencies. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I92e449245246452a0227cbd13f9c082e2088bf8c
2022-12-08IVGCVSW-7168 Add Conv2d and Constant support to TOSA Reference BackendMatthew Sloyan
* Added TOSA Conv2d and Constant mappings. * Added unique naming to mappings based on previous and following layers, so they are connected correctly. * Updated existing mappings with new naming convention. * Added all mappings to one main block in OptimizeSubgraphView. * Removed isMain from mapping functions. * Added Conv2d EndToEnd test. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I27c3e238407c32379ce25a1f01dad11523ef5d2b
2022-12-07IVGCVSW-6853 Rewrite BuildArmComputePermutationVector()Teresa Charlin
* Some pemutation vectors were not converted correctly. * Add Transpose end to end test. * Comments added with an example to clarify the differences betweeen Transpose and Permute Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6c0954ca6ce00ef5f2a6f3625abe6f4fd27b5cdf
2022-12-05IVGCVSW-4926 Add support in CpuRef implementation for Gather for axis ↵Nikhil Raj
different to 0 !android-nn-driver:8727 Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I4336007ad5a8552f7893ce6253f93cf9d1f5474f
2022-11-16IVGCVSW-7214 Disable BF16-Turbo-Mode and remove conversion layersRyan OShea
- Remove Bf16ToFp32 Conversion Layer - Remove Fp32ToBf16 Conversion Layer - Remove B16 Conversion tests * Throw exception if m_ReduceFp32ToBf16 optimzer option is set to true * Provide comments to enable fast math in order to use bf16 * Update docs to inform users to enable fast math for bf16 Execute Network Changes * Require bf16_turbo_mode to also have fast_math_enabled set to true - Remove setting m_ReduceFp32ToBf16 optimizer option Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: Ibaa6da9d29c96a1ce32ff5196b0847fde9f04a1c
2022-11-09IVGCVSW-7318 Support basic addition model in the TOSA Reference BackendRyan OShea
* Create Simple Addition EndtoEnd test * Create EndToEndTest file in TosaRef/test directory * Add AdditionEndToEnd test to CpuRef,CpuAcc,GpuAcc,TosaRef Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: Ic44e2b457c25dcb41bb3b17c05cce0e74bf17a80
2022-11-01IVGCVSW-6496 Add EndToEnd Layer test for Batch MatMul WorkloadTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6a541db9a602609282cc6f33af930ca141b83c41
2022-10-19MLCE-545 INT8 TFLite model execution abnormalKeith Davis
* Bug fix where files were being overwritten at each debug layer Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I609fdc82afcee925824efb02183c7dbc942fced0
2022-10-19MLCE-545 INT8 TFLite model execution abnormalKeith Davis
* Add functionality to print output tensors to file in tempdir * UnitTests Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: Idfb4c186544187db1fecdfca11c662540f645439
2022-09-07IVGCVSW-7159 Implement simple TOSA Reference Backend skeletonFrancis Murtagh
* Added files based on RefBackend * Added PreCompiled Workload skeleton * Increment ABI version of armnnTestUtils for CreateInput which had been left as pure virtual, added base implementation for it. * Add IsTosaLayerSupported() for Addition Change-Id: I4c963adf3f50593d17ecdf21554502a64ad3bd76
2022-08-30IVGCVSW-7105: BatchMatMul Optional Parameter SupportSamuel Yap
* Added transpose parameters to pre-transpose each input tensor's slices * Added adjoint parameters to pre-adjoint each input tensor's slices * Small refactoring (BatchMatMulDescriptor static helpers and BatchMatMulImpl constructor) * Updated input validation and output shape inference for parameters * Additional layer unit tests for parameters added * Versionings incremented Signed-off-by: Samuel Yap <samuel.yap@arm.com> Change-Id: Ibe5242a8a5bf604c13de0dc65844fd6c421cc667
2022-08-05IVGCVSW-7111 change backend deprecation from 22.11 to 23.08Jim Flynn
Signed-off-by: Jim Flynn <jim.flynn@arm.com> Change-Id: I3a3aab7b5042349cb2df8517678306665e037610
2022-08-05IVGCVSW-7145: BatchMatMul Fix for Raspi Cross Compile FailingSamuel Yap
* Changed long variable declaration to int Signed-off-by: Samuel Yap <samuel.yap@arm.com> Change-Id: I2df6f8f6df8780e48e09f7e68c04626a8a8a207d
2022-08-05GitHub #667: Neon fold padding into average pool 2D quantization bug fix.Cathal Corbett
* Originated from a GitHub issue: https://github.com/ARM-software/armnn/issues/667 * Initially, Arm NN supports the pool 2D operation because there is no padding on the pool2d. Neon failure occurs when padding is followed by average pool 2D due to folding optimization. * Here we prevent the folding optimization from happening for the above special case and add it in as a backend specific optimization. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ia0fd90c3a6b4b9d29c81106f154617d2e893e26b
2022-07-27IVGCVSW-7109: Add Batch MatMul front end support - ReferenceSamuel Yap
* Descriptors added for BatchMatMul * Layer definition added * Input validation added (will likely change when opt. param support comes in) * Ref workload implementation for BatchMatMul added (will also change with opt. param support) * Ref layer tests made for BatchMatMul * CMake and other build files updated Signed-off-by: Samuel Yap <samuel.yap@arm.com> Change-Id: Ic885301da543ee0fbe7922b85e7f9658c4efc617
2022-07-27IVGCVSW-6620 Update the async api to use ExecutionDataMatthew Sloyan
* ExecutionData holds a void* which can be assigned to data required for execution in a backend. WorkingMemDescriptors are used in the Ref backend which hold TensorHandles for inputs and outputs. * Updated ExecuteAsync functions to take ExecutionData. * Added CreateExecutionData and UpdateExectutionData to IBackendInternal. * Streamlined experimental IWorkingMemHandle API by removing map related function and unused m_workingMemDescriptorMap from WorkingMemHandle. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I54b0aab12872011743a141eb42dae200227769af
2022-05-24Tidy up some code in the reference backendMatthew Bentham
Make some things private that don't need to be public in RefElementwiseWorkload. Remove non-workload header files from RefWorkloads.hpp - the non-workload header files are implementation detail of individual workloads, whereas RefWorloads.hpp should only contain the workload definitions, needed for RefWorkloadFactory. Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: I4c28963a027162a6560e56cf84b6c0063283e48f
2022-05-18Remove use of PostAllocationConfigure from ExecuteAsync callsFinn Williams
* Resolves: IVGCVSW-6952 Signed-off-by: Finn Williams <finn.williams@arm.com> Change-Id: Ic85bd5267cf94e0ee8461ff4e62b9db3cb80877a
2022-05-16Github issue #643 remove use of deprecated standard templatesMatthew Bentham
Remove use of std::unary_function and std::binary_function which were deprecated in C+11. Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: I9e4624f570b475595c9e28bdf185ddcc2ddceb2f
2022-05-16IVGCVSW-6124 ConstTensorsAsInput: Conv2d - FrontEndKeith Davis
* Update Front-end and Tools. * Updated Serializer, Deserializer and unit tests to reflect this. * Updated TfLiteDelegate, TfLiteParser and OnnxParser. * Updated Ref. * Fixed resulting Neon / CL tests * Unified optimizers for conv2d ops * Optimizer Fix - Fp32ToBf16 * Partial implementation for ACL backends to fix VTS failures !android-nn-driver:7477 Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I5fb18877f7ee32643e15a9818945356274bb401b
2022-05-12Remove unused function PostAllocationConfigure() from IVGCVSW-6949.Cathal Corbett
* Addressing unresolved comment. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ia70999582670f2b521e9e2c891831618e476024f
2022-05-11IVGCVSW-6949 Remove use of member variables in RefDepthwiseConv2d workloadTeresa Charlin
* Fixes Segmentation fault in RefDepthwiseConvolution2d workload originated by IVGCVSW-6127 ConstTensorsAsInput DepthwiseConvolution2d Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I019377777ae384bcd193ecab7b8cdf8266e79f45
2022-05-10IVGCVSW-6936 Sqrt for CpuRef, CpuAcc and GpuAccTeresa Charlin
* Add Unit Tests * Bug Fix: add Sqrt to Neon and Cl workload factories Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I0db1d813a4e7d15431e87e825e6d14e61f5ffb7d
2022-05-05IVGCVSW-6127 ConstTensorsAsInput: DepthwiseConvolution2dCathal Corbett
!android-nn-driver:7418 * Update Front-end and Tools. * Updated Serializer, Deserializer and unit tests to reflect this. * Updated TfLiteDelegate, TfLiteParser and OnnxParser. * Change NNDriver to new API. * Updated Ref. * Neon and Cl backend partially completed (Backend.cpp files). * Added dynamic or constant input EndToEnd tests. * Added ConstantTensorAsInputMemeberVariableRedirect Optimization. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ib18b6c10a093042e165e25237dc04a4c67ba82da
2022-05-05Revert "IVGCVSW-6937 Add INT32 support to FLOOR"Teresa Charlin
This reverts commit 38b72e8de898d84a1481e242803da61009719891. * It is not longer needed as this functionality is cover with the commit: IVGCVSW-6938 Do not add Floor when FloorDiv is int32 in Tfliteparser Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Iac757cf9b47d2516804dca2efb347cfbd3282f14
2022-05-05IVGCVSW-6806 Add Unidirectional Sequence Lstm support to NeonMike Kelly
* Corrected TensorInfo order for IsUnidirectionalSequenceLstmSupported * outputStateOut TensorInfo is not optional. * cellStateOut TensorInfo is not optional. * TensorInfo Order matches other QLSTM/LSTM layers. * Added missing parameters to UnidirectionalSequenceLstmOperator for delegate. * Added quantized UnidirectionalSequenceLstm support to Neon !android-nn-driver:7457 Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I26dde1bb96793dd25eb9081ca5ae5f63752288c4
2022-05-04IVGCVSW-6937 Add INT32 support to FLOORTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6f7cddb2d23c67ae682132d18f98776c074dcb3b
2022-05-03IVGCVSW-6856 Add GATHERNd FrontEnd and Ref ImplementationTeresa Charlin
* Add front end * Add reference workload * Add unit tests * Add EndToEnd test Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I4cebd17b18476df86162e2dda3366c10e80bd2f8
2022-04-13IVGCVSW-6174 Add Cl Pooling3d WorkloadRyan OShea
* Add IsSupported for Pooling3d * Add CreateWorkload case for Pooling3d * Create new ClPooling3dWorkload header and source files * Add Pooling3d workload to ClWorkloads.hpp * Add tests for Pooling3d workload * Add Pooling3d build function to ArmComputeTensorUtils Change-Id: Ia270b0fe809a171ed73af14376de8708b346d500 Signed-off-by: Ryan OShea <ryan.oshea3@arm.com>
2022-04-11GitHub #634 Remove unused variable from Stack.cppTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I47ab4264f2f5a2209b669da125395b386efa17df
2022-04-11IVGCVSW-6707 Enables a bare metal compileJim Flynn
Change-Id: Icc2f83c5f27f413758fee3e5c1445e9fc44f42c8 Signed-off-by: Jim Flynn <jim.flynn@arm.com>
2022-03-23IVGCVSW-6706 Move headers to profiling/client/includeJim Flynn
!android-nn-driver:7337 Change-Id: Ide401623829cc99fb9b51e9bbce3482ce706a8dd Signed-off-by: Jim Flynn <jim.flynn@arm.com>
2022-03-08IVGCVSW-6772 Eliminate armnn/src/backends/backendsCommon/test/MockBackend.hppCathal Corbett
Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ie99fe9786eb5e30585f437d0c6362c73688148db
2022-03-03Revert "Revert "IVGCVSW-6268 Add support of Unidirectional Sequence Lstm ↵Cathal Corbett
fp32/fp16 to Neon"" This reverts commit f87b90e4dbb906436cf205a2a19e199bfe9224ed. Reason for revert: 22.02 release. Change-Id: I1ca5a79a8957908f655a6c4e79eefa24c5aec645
2022-02-23IVGCVSW-6803 Add int32 support for CONCATENATION in CpuRefTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Id9decafcebb6dbcac3a03516281524f22419cbfb
2022-02-23Revert "IVGCVSW-6268 Add support of Unidirectional Sequence Lstm fp32/fp16 ↵Cathal Corbett
to Neon" This reverts commit b0baff73b1574a198e57d46fcd704cedc43cea16. Reason for revert: cannot update ACL pin until 22.02 release. Change-Id: I049a125ba3b6a9b1cd6514ef9dd14d807773ed00
2022-02-21IVGCVSW-6268 Add support of Unidirectional Sequence Lstm fp32/fp16 to NeonCathal Corbett
!ComputeLibrary:7150 Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I3de48ffc8d08c95a22705e2b68d069791bddae73
2022-02-16Refactor Forced ImportFinn Williams
* Find and replace all workloads associated with imported IO * Only attempt tensorhandle replacement if supported by all workloads * Add new RefBaseWorkload to enable forced input for ref backend * Store imported tensorhandles in preImportedTensorhandles instead of outputHandles * Create pre-imported tensorhandles at network load-time * Front load import workload validation to load network time * Only call ReplaceTensorHandle when needed Change-Id: I3816a71b7f57ae90388bb16462a75d4ef3544fa7 Signed-off-by: Finn Williams <finn.williams@arm.com>
2022-02-11Fix unit test where NeonMemoryManager was used instead of RefMemoryManagerMatthew Bentham
Although the Neon and Ref backends can use each other's TensorHandles, their TensorHandleFactories can't use each other's MemoryManagers. Incorrectly passing the NeonMemoryManager to the RefTensorHandleFactory in unit test utility code resulted in an incorrect static_pointer_cast and a warning from the Undefined Behaviour Sanitizer. This change fixes the test code, and replaces use of static_pointer_cast with armnn::PolymorphicPointerDowncast which will check that the cast is legal in debug builds. Also, remove MockWorkloadFactoryHelper.hpp as it is unused. Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: I2b425e86fccacd7cc5ff186521fc6e53e7e50c77
2022-02-08IVGCVSW-6700 Fix segfaultDavid Monahan
* Update how we are setting the m_InputWorkloadSlotPairs to properly identify inputs Signed-off-by: David Monahan <David.Monahan@arm.com> Change-Id: I6d36f6d2bfdd42ade22c34e215f0d18b02702207
2022-02-07IVGCVSW-6635 Move MemCopyTestImpl from acl to armnnTestUtils.Colm Donelan
* Move MemCopyTestImpl.hpp from src/backends/aclCommon/test/ to include/armnnTestutils. * Refactor MemCopyTests in aclCommon, cl and Neon. * Introduce RefMemCopyTests to exercise this utility in x86 builds. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I8824f013d3656658ed0a2904bb79384e3af68641
2022-02-07IVGCVSW-6698 EndToEnd tests on ref to ensure allocated data can be reusedDavid Monahan
Signed-off-by: David Monahan <David.Monahan@arm.com> Change-Id: I2cda579d18be765fbc2783d9fd80ff8e5372a8a8
2022-02-03IVGCVSW-6696 Add Forced Import EndToEnd tests to Ref, Neon, and CLDavid Monahan
* Created EndToEnd tests with Misaligned buffers but import is forced * Added the Aligned Tests from a previous patch to avoid merge conflicts * Previous Aligned EndToEnd test for ref has been added to backendsCommon and is now used for neon as well * Added to Ref, Neon, and Gpu Backends * Neon tests only check for copies as reconfigure has not been implemented for the Neon backend yet Signed-off-by: David Monahan <David.Monahan@arm.com> Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I12ddf5780201044834d6d1bbeebce60a4614efd1
2022-01-31IVGCVSW-6552 Add support of aligned host memoryNarumol Prangnawarat
* Add AllocatedData functions to OutputHandler * Enable import aligned memory in ImportInputs * Enable import aligned memory in ImportOutputs * Allow to import input and output if the memory is aligned * Implement Reconfigure function on ClConvolution2dWorkload * End-to-end test on Ref and Cl to ensure that input and output memory are imported when aligned Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I9e5e4c26d1ac2f1d806803ade5f64c6479c51718
2022-01-25IVGCVSW-6676 Register CopyAndImportFactoryPairs to RefBackend and unit testsNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I9d695418fe240b7115a1c624abcd459f1459301b
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