aboutsummaryrefslogtreecommitdiff
path: root/src/backends/reference/workloads/RefDetectionPostProcessWorkload.cpp
AgeCommit message (Collapse)Author
2022-02-16Refactor Forced ImportFinn Williams
* Find and replace all workloads associated with imported IO * Only attempt tensorhandle replacement if supported by all workloads * Add new RefBaseWorkload to enable forced input for ref backend * Store imported tensorhandles in preImportedTensorhandles instead of outputHandles * Create pre-imported tensorhandles at network load-time * Front load import workload validation to load network time * Only call ReplaceTensorHandle when needed Change-Id: I3816a71b7f57ae90388bb16462a75d4ef3544fa7 Signed-off-by: Finn Williams <finn.williams@arm.com>
2021-05-06IVGCVSW-5815 Generalise ConstCpuTensorHandleJames Conroy
* Generalises ConstCpuTensorHandle and inherited classes by removing 'Cpu' from aliases. * New renamed classes: ConstTensorHandle, TensorHandle, ScopedTensorHandle, PassthroughTensorHandle, ConstPassthroughTensorHandle. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I1824e0e134202735fb77051f20a7252f161dfe16
2021-04-29IVGCVSW-5775 'Add Async Support to ExecuteNetwork'Sadik Armagan
* Enabled async mode with '-n, concurrent' and 'simultaneous-iterations' in ExecuteNetwork * Number of input files provided should be equal to number of input files provided multiply by number of simultaneous iterations divided by comma !armnn:5443 Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ibeb318010430bf4ae61a02b18b1bf88f3657774c
2021-04-14IVGCVSW-5787 Add/Update Execute() implementations in RefActivationWorkloadFinn Williams
* Added multithreaded StridedSliceEndToEndTest Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I4579db7b5959e0a22256f1bda00238c22e611dec
2019-07-02IVGCVSW-3307 Introduce RefTensorHandleMatthew Bentham
Use it for intermediate tensors on reference backend. Lays the groundwork for memory management in the reference backend. Change-Id: I7d3ee132cac31bde70ae6e1b815f4f0b03d550a6 Signed-off-by: Matthew Bentham <Matthew.Bentham@arm.com>
2019-06-05IVGCVSW-2971 Support QSymm16 for DetectionPostProcess workloadsAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I8af45afe851a9ccbf8bce54727147fcd52ac9a1f