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2022-06-27IVGCVSW-6981 Remove deprecated code 22.05 [Post Release]Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I9ccaefbe28ea572e9e2b4a2168574804667f7460
2022-06-27Update ACL pin to 41eb2d92c89274200d59ff97653e2bd66819b310Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ie21de47123578f7f316ce03882b0a93d2b01b9e4
2022-06-26IVGCVSW-6989 'Fixed build issue'Sadik Armagan
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I20e22821b6d4532953ddec2a8eac2a0f09e8013b
2022-06-24Update ACL pin to 700b913ed9257c44147372378bc8a0dadcfd2ac2Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I21b9d5e9b81fab3dc5984d529ff8b24605a17119
2022-06-24IVGCVSW-6958 'Integrate Import Host Memory to POINTER memory type'Sadik Armagan
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I8b05fb1e6ba31e46bf23ebfdaf55142dbe17980e
2022-06-23NNXSW-3858: Get non-const IConnectableLayer from I/O slotsNabeel Ahmad
* Added non-const variants of existing const member functions in IInputSlot and IOutputSlot to retrieve non-const IConnectableLayer Signed-off-by: Nabeel Ahmad <nabeel.ahmad@arm.com> Change-Id: Ic3388b578324edb4d2cca36acce6560ad1ce83c5
2022-06-23Update ACL pin to 14ce09453682618a53544152c3fe8efd5fa7b2c9Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I7e7174d35333121649f7d163a409a254d64b9b07
2022-06-22Revert "Revert "IVGCVSW-6873 Import inputs but don't export outputs fails.""Francis Murtagh
This reverts commit a0f8b15d4ddb5075f380003ff31b271d389d3b66. Reason for revert: <Test ClDmaBufInternalTests review > Change-Id: Ibc4a77fa008643849da7330391942e4c87b941e2
2022-06-21IVGCVSW-6954 'Fixed test failures on Conv2d"Sadik Armagan
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ifd5ad4d4ca553e3f58ea246a0ac3c6e6b8b31215
2022-06-21Revert "IVGCVSW-6873 Import inputs but don't export outputs fails."James Conroy
This reverts commit 03bf98a8bc51ad20eef4b9ca5fbf6ce15e063721. Reason for revert: Caused failures in tests located in internal repo. Change-Id: If35cb0ede349b270e4e7827324382e09455d8cfa
2022-06-20IVGCVSW-6873 Import inputs but don't export outputs fails.Colm Donelan
Only one bool is used to indicate whether inputs should be imported. However, its possible for the user to want to import inputs but not export outputs. In addition it's possible for a user to enabled import during optimize but then pass a memory source that does not require import. * Add m_ExportEnabled to INetwork.hpp. * Modify Network::dNetwork to consider both m_ImportEnabled and m_ExportEnabled. * Add ValidateSourcesMatchOptimizedNetwork to LoadedNetwork to validate import options between optimize and network load. * Update the TfLite delegate consider exportEnabled flag in the optimizer. !armnn-internal-tests:425350 Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I776eab81595898e43f91ab40306962eae61329f4
2022-06-20IVGCVSW-6989 "Merged experimental/armnn_shim_sl"Sadik Armagan
* Updated Serializer CMakeLists.txt to build armnnSerializerObj * Added constant tensors as input support to SL Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I22f6cf50147d99a01f7fe70d7446b114a4c57af3
2022-06-17Update Doxygen project number for 22.05 patch releaseNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: If22b8fb0013c70fe228fdba446e34962ae5fc421
2022-06-16Update ACL pin to 586fff9f1e30ad06b52aec3332f956cc25cfe56fNikhil Raj
Signed-off-by: Nikhil Raj <nikraj01@e126673.cambridge.arm.com> Change-Id: I80e7bb6810edb04b9b6df4972fd05a1c6180f087
2022-06-15GitHub 653: Segfault when parsing Unidirectional Sequence LSTMMike Kelly
* Fixed Segfault when parsing Unidirectional Sequence LSTM Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Ic69a4190c60ef595be64bc2c356e540319381b7e
2022-06-15IVGCVSW-6946 Add Pool3D to tflite delegateRyan OShea
* Add new test and test helper for Pool3d * Add new custom operator to switch in armnn_delegate.cpp * Add new pool3d function to pooling.hpp * Update doxygen Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: I77a541bf423b337c749e70c564cdd727efe2fd05
2022-06-14Update ACL pin to 894659a98e76d84bf209da27d8ecb6d9ed05b13dNikhil Raj
Signed-off-by: Nikhil Raj <nikraj01@e126673.cambridge.arm.com> Change-Id: If495a7af98aeb9f731c2f72ae43be01b51f83872
2022-06-13Update ACL pin to c3bc093552158165381f8c642004ed20b8fd99b2Teresa Charlin
* Fix crash in CpuActivationKernel Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib451e7091babcc0f59382deb2cd3708f701724e6
2022-06-10IVGCVSW-6986 SLTS Failures due to Caching commitsCathal Corbett
* Fix made to experimental/armnn_shim_sl branch also required for armnn master branch. * TestGenerated/GeneratedTests.Sync/argmax_1 fix. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Idb0324ff59e1ed13caf5f4bf899d1d3220d823d4
2022-06-08Update ACL pin to fe1b1f6d94c196f086122613277ff95062a7e834Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ia72b83f3cbcf90b4ea47f7475e6ed2e9358f8169
2022-05-30Update ACL pin to fdb534293b84182a89a78b5086cf05c07ef970e8Nikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Id3f1b100bdedf975e008e8f66e08747f8d8ae294
2022-05-26GitHub #644 fails to build with flatbuffers 2.0.6Mike Kelly
* Removed the pre-generated ArmnnSchema_generated.h * This version was generated using flatbuffers v1.12.0 and it contains code that's incompatible with newer versions * Android.mk will look for ArmnnSchema_generated.h in the armnnGenerated directory in the armnn directory. * The Serializer and Deserializer will look for ArmnnSchema_generated.h in the armnnGenerated directory. !android-nn-driver:7626 Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I13ff6b6c78740cf1f82750f56caab83200e6a3e5 Signed-off-by: Mike Kelly <mike.kelly@arm.com>
2022-05-24IVGCVSW-6255 Investigate and fix running mobilebert with the TfLiteDelegate ↵Cathal Corbett
(CpuRef) * Fixed bug occuring in Ref Gather Workload. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I3ee79f475fd9909bfbd4afb58f698439f26d6d65
2022-05-24GitHub #644 Fixed build warningsMike Kelly
* Deserializer.cpp * Length() has been deprecated in flatbuffers v.1.12.0 or earlier. * SerializerTests.cpp * armnn::BaseDescriptor& descriptor is unused. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Icf0f09863f13dfd86c2c209c36c7f74f194c707b
2022-05-24Tidy up some code in the reference backendMatthew Bentham
Make some things private that don't need to be public in RefElementwiseWorkload. Remove non-workload header files from RefWorkloads.hpp - the non-workload header files are implementation detail of individual workloads, whereas RefWorloads.hpp should only contain the workload definitions, needed for RefWorkloadFactory. Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: I4c28963a027162a6560e56cf84b6c0063283e48f
2022-05-24IVGCVSW-6550 Synchronize include/armnn and PyArmNN swig modules.Colm Donelan
* armnn_network.i: IVGCVSW-6127 ConstTensorsAsInput: DepthwiseConvolution2d. * armnn_descriptors.i: IVGCVSW-6127 ConstTensorsAsInput: DepthwiseConvolution2d. MLCE-604 Add Unidirectional Sequence Lstm support to TFLite. MLCE-530 Add support for UnidirectionalSequenceLstm to RefWorkload Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I0c054db17dbf9a1eb14c12d1fd1337f8003a92d3
2022-05-24IVGCVSW-6967 Add Optimizer Test for FullyConnected in Fp32ToBf16experimental/serializationIssueKeith Davis
* Test already existed but bias was not enabled so yielded false positive * Updated Conv2d and FC to have const layers as inputs Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: Id4193adef2ac67b3a4681345e4dc01414cbbbad7
2022-05-23MLCE-825: Give reason when workload unsupported for Non Constant Weights/BiasFrancis Murtagh
* BackendHelper.cpp IsXXXLayerSupported doesn't get as far as Neon/Cl Validate functions where arm_compute::Status is returned. * Conv2d, Depthwise, DilatedDepthwise and FullyConnected * Tidy up if() -> if () * Clean up logic in FullyConnected so that isLayerSupported gets called Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I5da1a882f4a2f55e90aa984b2b9548a847cb3a2d
2022-05-23IVGCVSW-6123 ConstTensorsAsInputs: Conv2dKeith Davis
* Use new INetwork::AddConvolution2dLayer instead of deprecated version * Remove duplicated test in SerlializerTests * Fix some cosmetics Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I3407815bfdc1cdc01ca0a667b8e4d80d8621783f
2022-05-20Improve front-facing documentationJames Conroy
* Cleanup and make homepage docs more concise and direct * Highlight use of the TF Lite Delegate, guides and AI Tech talk Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I7d0221bf804dd1769568beccbca93d23cdba24b6
2022-05-19IVGCVSW-6145 ConstTensorsAsInput: Optimizer Fix - GetConstantTensorsByRefFrancis Murtagh
* Add functionality to check for ConstantTensorsAsInputs to GetConstantTensorsByRef * Reorder optimizations so RedirectMembersToConstantInputs occurs after Conversion of Constants * Ensure graph is in topological order after loading in OptimizedNet * Fixed test to check release of m_LayerOutputs. Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I7cff50798d7217e8ea0d2f9b153eabd10174a566
2022-05-18IVGCVSW-6147 ConstTensorsAsInput: Optimizer - FusePermuteIntoConstLayerCathal Corbett
* No trailing permute layer after a constant layer * Unit test for optimization Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I0d098f5af41d2c55df7cef1ccfb848093320ddc1
2022-05-18IVGCVSW-6455 Support Const + Dequantize layer and optimize it.Teresa Charlin
* Support Float16 as input to Dequantize layer * Add Optimization to substitute Const+Dequantize layers with Const layer Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I58bb7e3871ca480c7b6fca93c4efb2de84e09e64 Signed-off-by: David <david.monahan@arm.com>
2022-05-18IVGCVSW-6929 Support for models with implicit expandedMike Kelly
dimensions * Added allow-expanded-dims to TFLite parser and ArmNN delegate * If true ArmNN will disregard dimensions with a size of 1 when validating tensor shapes. Tensor sizes must still match. * This allows us to support models where tensors have expanded dimensions (i.e. extra dimensions with a size of 1). * Fixed bug in Network where it assumed that only the first option could be ShapeInferenceMethod. * Fixed bug where m_ShapeInferenceMethod was lost when copying or moving Graphs. * Changed Delegate to pass "infer-output-shape", "allow-expanded-dims" and other BackendOptions through to the Network during construction. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Ibe7c5ae6597796fc9164cb07bd372bd7f8f8cacf
2022-05-18Remove use of PostAllocationConfigure from ExecuteAsync callsFinn Williams
* Resolves: IVGCVSW-6952 Signed-off-by: Finn Williams <finn.williams@arm.com> Change-Id: Ic85bd5267cf94e0ee8461ff4e62b9db3cb80877a
2022-05-18BugFix: Overload Deprecated IsUnidirectionalSequenceLstmSupportedFrancis Murtagh
* Signature change is ABI/API break, overloaded and forwarded to new function. Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I8590a6fd65986b5aeff905c1e761cb5c51042e99
2022-05-17IVGCVSW-6126 ConstTensorsAsInput: Conv2d - BackendsCathal Corbett
!android-nn-driver:7477 Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ibf633ccccc385bd980934ff829407d21981323ef
2022-05-16Github issue #643 remove use of deprecated standard templatesMatthew Bentham
Remove use of std::unary_function and std::binary_function which were deprecated in C+11. Signed-off-by: Matthew Bentham <matthew.bentham@arm.com> Change-Id: I9e4624f570b475595c9e28bdf185ddcc2ddceb2f
2022-05-16IVGCVSW-6124 ConstTensorsAsInput: Conv2d - FrontEndKeith Davis
* Update Front-end and Tools. * Updated Serializer, Deserializer and unit tests to reflect this. * Updated TfLiteDelegate, TfLiteParser and OnnxParser. * Updated Ref. * Fixed resulting Neon / CL tests * Unified optimizers for conv2d ops * Optimizer Fix - Fp32ToBf16 * Partial implementation for ACL backends to fix VTS failures !android-nn-driver:7477 Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I5fb18877f7ee32643e15a9818945356274bb401b
2022-05-16Update Project Number in DoxyfileNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I8d1584478983aeb68f65739a9ad3d4e5d3573a5c
2022-05-13IVGCVSW-6175 Add Pooling3d to NeonRyan OShea
* Add IsSupported for Pooling3d * Add CreateWorkload case for Pooling3d * Create new NeonPooling3dWorkload header and source files * Add Pooling3d workload to NeonWorkloads.hpp * Add float32 tests for Pooling3d workload * Add Uint8 tests for Cl and NE pooling3d Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: Ic992e1233d1eb8db52df2c8446183df1c907bc4d
2022-05-13IVGCVSW-6260 ConstTensorsAsInput: Fully Connected Cl and Neon support.Cathal Corbett
* IVGCVSW-6940 ConstTensorsAsInput: DepthwiseConvolution2d - Complete Neon and Cl Bug Fix * Bug fix to enable Cl and Neon Backend Compatibility ConstantTensorsAsInputs * Updated Cl and Neon FullyConnected workloads to handle constant weights and bias as inputs rather than reading from member variables. * Prevent non const weights and biases passing CL and NEON validate for Depthwise Convolution. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I0f505ff5998a183152f843d0f6cc74327ba920e7
2022-05-12Update ACL pin to branches/arm_compute_22_05Teresa Charlin
Change-Id: I2c23a8d7173b07aa8797a771489599762cba5a16 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
2022-05-12IVGCVSW-6940 ConstTensorsAsInput: DepthwiseConvolution2d - Complete ACLCathal Corbett
* Added backend specific optimization & test for CpuAcc and GpuAcc: PermuteDepthwiseConv2dWeights Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I600476b2e9c557a39818a574c1091c9d650b21b1
2022-05-12Remove unused function PostAllocationConfigure() from IVGCVSW-6949.Cathal Corbett
* Addressing unresolved comment. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ia70999582670f2b521e9e2c891831618e476024f
2022-05-11IVGCVSW-6949 Remove use of member variables in RefDepthwiseConv2d workloadTeresa Charlin
* Fixes Segmentation fault in RefDepthwiseConvolution2d workload originated by IVGCVSW-6127 ConstTensorsAsInput DepthwiseConvolution2d Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I019377777ae384bcd193ecab7b8cdf8266e79f45
2022-05-10IVGCVSW-6936 Sqrt for CpuRef, CpuAcc and GpuAccTeresa Charlin
* Add Unit Tests * Bug Fix: add Sqrt to Neon and Cl workload factories Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I0db1d813a4e7d15431e87e825e6d14e61f5ffb7d
2022-05-10IVGCVSW-6861 Add GATHERNd CL workloadTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I8ba7e56062c285c672dcaa9d13be319eb4f1fca6
2022-05-09IVGCVSW-6862 Use same datatype for all containers of indices in NeonGatherNdTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6b1c7c1c499dc93aa58fa9f58b64fb664e8bcc56
2022-05-06IVGCVSW-6929 Fix for segfault in tflite delegateMike Kelly
* It's possible that a model may have an input entry for bias tensors but that the index for those is -1. If it's -1 then it's not present. * Fixed logic error in IsOptionalOperandPresent: it returned false if it was present and true if it was missing. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I45ad8d8552122493c529b1a35a5689416ccfbb71
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