3 files changed, 29 insertions, 3 deletions
diff --git a/src/backends/reference/test/RefEndToEndTests.cpp b/src/backends/reference/test/RefEndToEndTests.cpp
index b6974811ef..521854b12b 100644
--- a/src/backends/reference/test/RefEndToEndTests.cpp
+++ b/src/backends/reference/test/RefEndToEndTests.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -25,6 +25,7 @@
 #include <backendsCommon/test/ResizeEndToEndTestImpl.hpp>
 #include <backendsCommon/test/SpaceToDepthEndToEndTestImpl.hpp>
 #include <backendsCommon/test/SplitterEndToEndTestImpl.hpp>
+#include <backendsCommon/test/StridedSliceAsyncEndToEndTest.hpp>
 #include <backendsCommon/test/TransposeConvolution2dEndToEndTestImpl.hpp>
 
 #include <boost/test/unit_test.hpp>
@@ -1336,6 +1337,10 @@ BOOST_AUTO_TEST_CASE(RefStridedSliceInvalidSliceEndToEndTest)
     StridedSliceInvalidSliceEndToEndTest(defaultBackends);
 }
 
+BOOST_AUTO_TEST_CASE(RefAsyncFP32StridedSlicedEndToEndTest)
+{
+    armnn::experimental::StridedSlicedEndToEndTest<armnn::DataType::Float32>(defaultBackends);
+}
 #endif
 
 BOOST_AUTO_TEST_SUITE_END()
diff --git a/src/backends/reference/workloads/RefStridedSliceWorkload.cpp b/src/backends/reference/workloads/RefStridedSliceWorkload.cpp
index 6a29439cc0..ce807ee087 100644
--- a/src/backends/reference/workloads/RefStridedSliceWorkload.cpp
+++ b/src/backends/reference/workloads/RefStridedSliceWorkload.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -35,4 +35,24 @@ void RefStridedSliceWorkload::Execute() const
                  GetDataTypeSize(inputDataType));
 }
 
+void RefStridedSliceWorkload::ExecuteAsync(WorkingMemDescriptor& descriptor)
+{
+    ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefStridedSliceWorkload_Execute_WorkingMemDescriptor");
+
+    const TensorInfo& inputInfo  = GetTensorInfo(descriptor.m_Inputs[0]);
+    const TensorInfo& outputInfo = GetTensorInfo(descriptor.m_Outputs[0]);
+
+    DataType inputDataType  = inputInfo.GetDataType();
+    DataType outputDataType = outputInfo.GetDataType();
+
+    ARMNN_ASSERT(inputDataType == outputDataType);
+    IgnoreUnused(outputDataType);
+
+    StridedSlice(inputInfo,
+                 m_Data.m_Parameters,
+                 descriptor.m_Inputs[0]->Map(),
+                 descriptor.m_Outputs[0]->Map(),
+                 GetDataTypeSize(inputDataType));
+}
+
 } // namespace armnn
diff --git a/src/backends/reference/workloads/RefStridedSliceWorkload.hpp b/src/backends/reference/workloads/RefStridedSliceWorkload.hpp
index 44aabc0106..3e253edcd9 100644
--- a/src/backends/reference/workloads/RefStridedSliceWorkload.hpp
+++ b/src/backends/reference/workloads/RefStridedSliceWorkload.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -15,6 +15,7 @@ class RefStridedSliceWorkload : public BaseWorkload<StridedSliceQueueDescriptor>
 public:
     RefStridedSliceWorkload(const StridedSliceQueueDescriptor& descriptor, const WorkloadInfo& info);
     void Execute() const override;
+    void ExecuteAsync(WorkingMemDescriptor& descriptor) override;
 };
 
 } // namespace armnn