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-rw-r--r--src/backends/cl/test/ClLayerTests.cpp72
-rw-r--r--src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp49
2 files changed, 99 insertions, 22 deletions
diff --git a/src/backends/cl/test/ClLayerTests.cpp b/src/backends/cl/test/ClLayerTests.cpp
index 10e2a54c9f..1ad1de8e04 100644
--- a/src/backends/cl/test/ClLayerTests.cpp
+++ b/src/backends/cl/test/ClLayerTests.cpp
@@ -109,6 +109,18 @@ ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat322,
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat323,
ClContextControlFixture,
BatchToSpaceNdNhwcTest3<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat324,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest4<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat325,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest5<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat326,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest6<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcFloat327,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest7<DataType::Float32>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat321,
ClContextControlFixture,
@@ -119,6 +131,18 @@ ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat322,
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat323,
ClContextControlFixture,
BatchToSpaceNdNchwTest3<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat324,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest4<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat325,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest5<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat326,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest6<DataType::Float32>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwFloat327,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest7<DataType::Float32>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt1,
ClContextControlFixture,
@@ -129,6 +153,18 @@ ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt2,
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt3,
ClContextControlFixture,
BatchToSpaceNdNhwcTest3<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt14,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest4<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt5,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest5<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt6,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest6<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcInt7,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest7<DataType::QAsymmS8>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt1,
ClContextControlFixture,
@@ -139,6 +175,18 @@ ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt2,
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt3,
ClContextControlFixture,
BatchToSpaceNdNchwTest3<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt4,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest4<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt5,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest5<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt6,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest6<DataType::QAsymmS8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwInt7,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest7<DataType::QAsymmS8>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint1,
ClContextControlFixture,
@@ -149,6 +197,18 @@ ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint2,
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint3,
ClContextControlFixture,
BatchToSpaceNdNhwcTest3<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint4,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest4<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint5,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest5<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint6,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest6<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNhwcUint7,
+ ClContextControlFixture,
+ BatchToSpaceNdNhwcTest7<DataType::QAsymmU8>)
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint1,
ClContextControlFixture,
@@ -159,6 +219,18 @@ ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint2,
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint3,
ClContextControlFixture,
BatchToSpaceNdNchwTest3<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint14,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest4<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint5,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest5<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint6,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest6<DataType::QAsymmU8>)
+ARMNN_AUTO_TEST_FIXTURE_WITH_THF(BatchToSpaceNdNchwUint7,
+ ClContextControlFixture,
+ BatchToSpaceNdNchwTest7<DataType::QAsymmU8>)
// Fully Connected
ARMNN_AUTO_TEST_FIXTURE_WITH_THF(SimpleFullyConnected,
diff --git a/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp b/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp
index 8a9a33b16b..ad3a602f48 100644
--- a/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp
+++ b/src/backends/cl/workloads/ClBatchToSpaceNdWorkload.cpp
@@ -1,5 +1,5 @@
//
-// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2017, 2023 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
@@ -17,6 +17,29 @@ namespace armnn
{
using namespace armcomputetensorutils;
+arm_compute::Status ClBatchToSpaceNdWorkloadValidate(const TensorInfo& input,
+ const TensorInfo& output,
+ const BatchToSpaceNdDescriptor& descriptor)
+{
+ DataLayout dataLayout = descriptor.m_DataLayout;
+ const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, dataLayout);
+
+ // ArmNN blockShape is [H, W] Cl asks for W, H
+ int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[0]);
+ int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
+
+ const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, dataLayout);
+
+ const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor);
+
+ const arm_compute::Status aclStatus = arm_compute::CLBatchToSpaceLayer::validate(&aclInputInfo,
+ blockWidth,
+ blockHeight,
+ &aclOutputInfo,
+ cropInfo);
+ return aclStatus;
+}
+
ClBatchToSpaceNdWorkload::ClBatchToSpaceNdWorkload(const BatchToSpaceNdQueueDescriptor& descriptor,
const WorkloadInfo& info,
const arm_compute::CLCompileContext& clCompileContext)
@@ -42,9 +65,11 @@ ClBatchToSpaceNdWorkload::ClBatchToSpaceNdWorkload(const BatchToSpaceNdQueueDesc
arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
output.info()->set_data_layout(aclDataLayout);
+ const arm_compute::CropInfo cropInfo = BuildArmComputeCropInfo(descriptor.m_Parameters);
+
{
ARMNN_SCOPED_PROFILING_EVENT(Compute::Undefined, "ClBatchToSpaceNdWorkload_configure");
- m_Layer.configure(clCompileContext, &input, blockWidth, blockHeight, &output);
+ m_Layer.configure(clCompileContext, &input, blockWidth, blockHeight, &output, cropInfo);
}
}
@@ -54,24 +79,4 @@ void ClBatchToSpaceNdWorkload::Execute() const
RunClFunction(m_Layer, CHECK_LOCATION());
}
-arm_compute::Status ClBatchToSpaceNdWorkloadValidate(const TensorInfo& input,
- const TensorInfo& output,
- const BatchToSpaceNdDescriptor& descriptor)
-{
- DataLayout dataLayout = descriptor.m_DataLayout;
- const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, dataLayout);
-
- // ArmNN blockShape is [H, W] Cl asks for W, H
- int32_t blockHeight = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[0]);
- int32_t blockWidth = armnn::numeric_cast<int32_t>(descriptor.m_BlockShape[1]);
-
- const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output, dataLayout);
-
- const arm_compute::Status aclStatus = arm_compute::CLBatchToSpaceLayer::validate(&aclInputInfo,
- blockWidth,
- blockHeight,
- &aclOutputInfo);
- return aclStatus;
-}
-
} //namespace armnn
generated by cgit v1.2.1 (git 2.23.0) at 2024-07-12 23:54:48 +0000