diff options
-rw-r--r-- | delegate/src/armnn_delegate.cpp | 12 | ||||
-rw-r--r-- | delegate/src/test/ElementwiseUnaryTest.cpp | 119 | ||||
-rw-r--r-- | docs/05_03_delegate.dox | 6 |
3 files changed, 135 insertions, 2 deletions
diff --git a/delegate/src/armnn_delegate.cpp b/delegate/src/armnn_delegate.cpp index 1b6d68eb7a..eac3862c18 100644 --- a/delegate/src/armnn_delegate.cpp +++ b/delegate/src/armnn_delegate.cpp @@ -722,6 +722,12 @@ TfLiteStatus ArmnnSubgraph::VisitNode(DelegateData& delegateData, tfLiteNode, nodeIndex, kTfLiteBuiltinLocalResponseNormalization); + case kTfLiteBuiltinLog: + return VisitElementwiseUnaryOperator(delegateData, + tfLiteContext, + tfLiteNode, + nodeIndex, + armnn::UnaryOperation::Log); case kTfLiteBuiltinLogicalAnd: return VisitLogicalBinaryOperator(delegateData, tfLiteContext, @@ -910,6 +916,12 @@ TfLiteStatus ArmnnSubgraph::VisitNode(DelegateData& delegateData, tfLiteNode, nodeIndex, kTfLiteBuiltinShape); + case kTfLiteBuiltinSin: + return VisitElementwiseUnaryOperator(delegateData, + tfLiteContext, + tfLiteNode, + nodeIndex, + armnn::UnaryOperation::Sin); case kTfLiteBuiltinSplit: return VisitSplitOperator(delegateData, tfLiteContext, diff --git a/delegate/src/test/ElementwiseUnaryTest.cpp b/delegate/src/test/ElementwiseUnaryTest.cpp index 3200423b10..4d48d6e2ed 100644 --- a/delegate/src/test/ElementwiseUnaryTest.cpp +++ b/delegate/src/test/ElementwiseUnaryTest.cpp @@ -1,5 +1,5 @@ // -// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // @@ -63,6 +63,26 @@ TEST_CASE ("Exp_Float32_GpuAcc_Test") ElementwiseUnaryFP32Test(tflite::BuiltinOperator_EXP, backends, inputValues, expectedOutputValues); } +TEST_CASE ("Log_Float32_GpuAcc_Test") +{ + // Create the ArmNN Delegate + std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc }; + // Set input data + std::vector<float> inputValues + { + 1.0f, 1.0f, 2.0f, + 3.0f, 4.0f, 2.71828f + }; + // Set output data + std::vector<float> expectedOutputValues + { + 0.f, 0.f, 0.69314718056f, + 1.09861228867f, 1.38629436112f, 0.99999932734f + }; + + ElementwiseUnaryFP32Test(tflite::BuiltinOperator_LOG, backends, inputValues, expectedOutputValues); +} + TEST_CASE ("Neg_Float32_GpuAcc_Test") { // Create the ArmNN Delegate @@ -103,6 +123,25 @@ TEST_CASE ("Rsqrt_Float32_GpuAcc_Test") ElementwiseUnaryFP32Test(tflite::BuiltinOperator_RSQRT, backends, inputValues, expectedOutputValues); } +TEST_CASE ("Sin_Float32_GpuAcc_Test") +{ + // Create the ArmNN Delegate + std::vector<armnn::BackendId> backends = { armnn::Compute::GpuAcc }; + // Set input data + std::vector<float> inputValues + { + 0.0f, 1.0f, 16.0f, + 0.5f, 36.0f, -1.f + }; + // Set output data + std::vector<float> expectedOutputValues + { + 0.0f, 0.8414709848f, -0.28790331666f, + 0.4794255386f, -0.99177885344f, -0.8414709848f + }; + + ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SIN, backends, inputValues, expectedOutputValues); +} } // TEST_SUITE("ElementwiseUnary_GpuAccTests") @@ -152,6 +191,26 @@ TEST_CASE ("Exp_Float32_CpuAcc_Test") ElementwiseUnaryFP32Test(tflite::BuiltinOperator_EXP, backends, inputValues, expectedOutputValues); } +TEST_CASE ("Log_Float32_CpuAcc_Test") +{ + // Create the ArmNN Delegate + std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc }; + // Set input data + std::vector<float> inputValues + { + 1.0f, 1.0f, 2.0f, + 3.0f, 4.0f, 2.71828f + }; + // Set output data + std::vector<float> expectedOutputValues + { + 0.f, 0.f, 0.69314718056f, + 1.09861228867f, 1.38629436112f, 0.99999932734f + }; + + ElementwiseUnaryFP32Test(tflite::BuiltinOperator_LOG, backends, inputValues, expectedOutputValues); +} + TEST_CASE ("Neg_Float32_CpuAcc_Test") { // Create the ArmNN Delegate @@ -192,6 +251,25 @@ TEST_CASE ("Rsqrt_Float32_CpuAcc_Test") ElementwiseUnaryFP32Test(tflite::BuiltinOperator_RSQRT, backends, inputValues, expectedOutputValues); } +TEST_CASE ("Sin_Float32_CpuAcc_Test") +{ + // Create the ArmNN Delegate + std::vector<armnn::BackendId> backends = { armnn::Compute::CpuAcc }; + // Set input data + std::vector<float> inputValues + { + 0.0f, 1.0f, 16.0f, + 0.5f, 36.0f, -1.f + }; + // Set output data + std::vector<float> expectedOutputValues + { + 0.0f, 0.8414709848f, -0.28790331666f, + 0.4794255386f, -0.99177885344f, -0.8414709848f + }; + + ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SIN, backends, inputValues, expectedOutputValues); +} } // TEST_SUITE("ElementwiseUnary_CpuAccTests") TEST_SUITE("ElementwiseUnary_CpuRefTests") @@ -239,6 +317,26 @@ TEST_CASE ("Exp_Float32_CpuRef_Test") ElementwiseUnaryFP32Test(tflite::BuiltinOperator_EXP, backends, inputValues, expectedOutputValues); } +TEST_CASE ("Log_Float32_CpuRef_Test") +{ + // Create the ArmNN Delegate + std::vector<armnn::BackendId> backends = { armnn::Compute::CpuRef }; + // Set input data + std::vector<float> inputValues + { + 1.0f, 1.0f, 2.0f, + 3.0f, 4.0f, 2.71828f + }; + // Set output data + std::vector<float> expectedOutputValues + { + 0.f, 0.f, 0.69314718056f, + 1.09861228867f, 1.38629436112f, 0.99999932734f + }; + + ElementwiseUnaryFP32Test(tflite::BuiltinOperator_LOG, backends, inputValues, expectedOutputValues); +} + TEST_CASE ("Neg_Float32_CpuRef_Test") { // Create the ArmNN Delegate @@ -298,6 +396,25 @@ TEST_CASE ("Sqrt_Float32_CpuRef_Test") ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SQRT, backends, inputValues, expectedOutputValues); } +TEST_CASE ("Sin_Float32_CpuRef_Test") +{ + // Create the ArmNN Delegate + std::vector<armnn::BackendId> backends = { armnn::Compute::CpuRef }; + // Set input data + std::vector<float> inputValues + { + 0.0f, 1.0f, 16.0f, + 0.5f, 36.0f, -1.f + }; + // Set output data + std::vector<float> expectedOutputValues + { + 0.0f, 0.8414709848f, -0.28790331666f, + 0.4794255386f, -0.99177885344f, -0.8414709848f + }; + + ElementwiseUnaryFP32Test(tflite::BuiltinOperator_SIN, backends, inputValues, expectedOutputValues); +} } // TEST_SUITE("ElementwiseUnary_CpuRefTests") } // namespace armnnDelegate
\ No newline at end of file diff --git a/docs/05_03_delegate.dox b/docs/05_03_delegate.dox index d1c41fe213..71754323bc 100644 --- a/docs/05_03_delegate.dox +++ b/docs/05_03_delegate.dox @@ -1,4 +1,4 @@ -/// Copyright (c) 2021 ARM Limited and Contributors. All rights reserved. +/// Copyright (c) 2022 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// @@ -89,6 +89,8 @@ The Arm NN SDK TensorFlow Lite delegate currently supports the following operato - LOCAL_RESPONSE_NORMALIZATION +- LOG + - LOGICAL_AND - LOGICAL_NOT @@ -151,6 +153,8 @@ The Arm NN SDK TensorFlow Lite delegate currently supports the following operato - SHAPE +- SIN + - SOFTMAX - SPACE_TO_BATCH_ND |