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author | mathad01 <matthew.haddon@arm.com> | 2021-04-07 12:07:30 +0100 |
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committer | mathad01 <matthew.haddon@arm.com> | 2021-04-12 15:31:28 +0100 |
commit | b392e9845b7f40ab0c389f29f13f6ec84dd814d1 (patch) | |
tree | d71d260f7ff5ba7498ea653174bd166f27865ee5 /src/backends/reference/workloads | |
parent | 35ad91c489312c23dddac5e6dffde840fbb85b79 (diff) | |
download | armnn-b392e9845b7f40ab0c389f29f13f6ec84dd814d1.tar.gz |
IVGCVSW-5410 Add front-end support for CAST
IVGCVSW-5415 Add TfLiteParser support for CAST
* Added front end support for CAST, including support in the
Reference workload, Serialization, Deserializtion, Unit tests, and
TfLiteParser.
Signed-off-by: mathad01 <matthew.haddon@arm.com>
Change-Id: Iaf670ca5912a21ed6bc84f7f83a68b42154846bb
Diffstat (limited to 'src/backends/reference/workloads')
4 files changed, 67 insertions, 0 deletions
diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt index 1f4298be5d..dadedf995a 100644 --- a/src/backends/reference/workloads/CMakeLists.txt +++ b/src/backends/reference/workloads/CMakeLists.txt @@ -63,6 +63,8 @@ list(APPEND armnnRefBackendWorkloads_sources RefBatchNormalizationWorkload.hpp RefBatchToSpaceNdWorkload.cpp RefBatchToSpaceNdWorkload.hpp + RefCastWorkload.cpp + RefCastWorkload.hpp RefComparisonWorkload.cpp RefComparisonWorkload.hpp RefConcatWorkload.cpp diff --git a/src/backends/reference/workloads/RefCastWorkload.cpp b/src/backends/reference/workloads/RefCastWorkload.cpp new file mode 100644 index 0000000000..7080415e5d --- /dev/null +++ b/src/backends/reference/workloads/RefCastWorkload.cpp @@ -0,0 +1,40 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "RefCastWorkload.hpp" +#include "RefWorkloadUtils.hpp" +#include <armnnUtils/FloatingPointConverter.hpp> +#include <ResolveType.hpp> +#include "Encoders.hpp" +#include "Decoders.hpp" + +namespace +{ + void Cast(armnn::Decoder<float>& in, armnn::Encoder<float>& out, const uint32_t numElements ) + { + for (unsigned int i = 0; i < numElements; i++) + { + out.Set(in.Get()); + ++in; + ++out; + } + } +} + +namespace armnn +{ + + void RefCastWorkload::Execute() const + { + ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefCastWorkload_Execute"); + const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]); + const TensorInfo& outputInfo = GetTensorInfo(m_Data.m_Outputs[0]); + + Cast(*MakeDecoder<float>(inputInfo, m_Data.m_Inputs[0]->Map()), + *MakeEncoder<float>(outputInfo, m_Data.m_Outputs[0]->Map()), + inputInfo.GetNumElements()); + } + +} //namespace armnn
\ No newline at end of file diff --git a/src/backends/reference/workloads/RefCastWorkload.hpp b/src/backends/reference/workloads/RefCastWorkload.hpp new file mode 100644 index 0000000000..6742ef08ca --- /dev/null +++ b/src/backends/reference/workloads/RefCastWorkload.hpp @@ -0,0 +1,24 @@ +// +// Copyright © 2021 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include <backendsCommon/Workload.hpp> +#include <backendsCommon/WorkloadData.hpp> +#include "RefWorkloadUtils.hpp" + +namespace armnn +{ + + +class RefCastWorkload : public BaseWorkload<CastQueueDescriptor> +{ +public: + using BaseWorkload<CastQueueDescriptor>::BaseWorkload; + void Execute() const override; +}; + +} //namespace armnn + diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp index 989644f633..d3995f2b82 100644 --- a/src/backends/reference/workloads/RefWorkloads.hpp +++ b/src/backends/reference/workloads/RefWorkloads.hpp @@ -18,6 +18,7 @@ #include "RefArgMinMaxWorkload.hpp" #include "RefBatchNormalizationWorkload.hpp" #include "RefBatchToSpaceNdWorkload.hpp" +#include "RefCastWorkload.hpp" #include "RefComparisonWorkload.hpp" #include "RefConvolution2dWorkload.hpp" #include "RefConstantWorkload.hpp" |