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| author | Sadik Armagan <sadik.armagan@arm.com> | 2020-04-17 12:45:14 +0100 |
|---|---|---|
| committer | TeresaARM <teresa.charlinreyes@arm.com> | 2020-04-27 14:49:42 +0000 |
| commit | 303980c502c721f13d65e7087be6c0758df65044 (patch) | |
| tree | f1a9ab898b3121b988b8328161eddeb6a608e73f /src/backends/reference/workloads/RefPadWorkload.hpp | |
| parent | 49c52a1e3be742cd7785ccc36c31cbbe495c4003 (diff) | |
| download | armnn-303980c502c721f13d65e7087be6c0758df65044.tar.gz | |
IVGCVSW-4668 Add TENSOR_QUANT8_ASYMM_SIGNED data type support to CpuRef operators
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
Change-Id: I094125ba80699cc3cf5226bda6662a54e6caa988
Diffstat (limited to 'src/backends/reference/workloads/RefPadWorkload.hpp')
| -rw-r--r-- | src/backends/reference/workloads/RefPadWorkload.hpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/backends/reference/workloads/RefPadWorkload.hpp b/src/backends/reference/workloads/RefPadWorkload.hpp index 5134ac8bff..74dcab1967 100644 --- a/src/backends/reference/workloads/RefPadWorkload.hpp +++ b/src/backends/reference/workloads/RefPadWorkload.hpp @@ -31,9 +31,10 @@ public: }; using RefPadBFloat16Workload = RefPadWorkload<DataType::BFloat16>; -using RefPadFloat32Workload = RefPadWorkload<DataType::Float32>; -using RefPadFloat16Workload = RefPadWorkload<DataType::Float16>; -using RefPadQAsymm8Workload = RefPadWorkload<DataType::QAsymmU8>; -using RefPadQSymm16Workload = RefPadWorkload<DataType::QSymmS16>; +using RefPadFloat32Workload = RefPadWorkload<DataType::Float32>; +using RefPadFloat16Workload = RefPadWorkload<DataType::Float16>; +using RefPadQAsymmS8Workload = RefPadWorkload<DataType::QAsymmS8>; +using RefPadQAsymm8Workload = RefPadWorkload<DataType::QAsymmU8>; +using RefPadQSymm16Workload = RefPadWorkload<DataType::QSymmS16>; } //namespace armnn |