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| author | Nattapat Chaimanowong <nattapat.chaimanowong@arm.com> | 2019-04-24 16:19:57 +0100 |
|---|---|---|
| committer | Matteo Martincigh <matteo.martincigh@arm.com> | 2019-04-29 11:04:20 +0000 |
| commit | ae2c5f0350a7033f58578f9c509345445a639865 (patch) | |
| tree | 4fd6266fc7d917130a0087938eafcadd1b7f31be /src/backends/reference/workloads/RefActivationWorkload.cpp | |
| parent | bb73e576e75fde75acb28362fb7be194dfcbcada (diff) | |
| download | armnn-ae2c5f0350a7033f58578f9c509345445a639865.tar.gz | |
IVGCVSW-2982 Refactor reference Activation workload
Change-Id: Ia3b9a56787cc68822a3c1635de82e03ecc0aae27
Signed-off-by: Nattapat Chaimanowong <nattapat.chaimanowong@arm.com>
Diffstat (limited to 'src/backends/reference/workloads/RefActivationWorkload.cpp')
| -rw-r--r-- | src/backends/reference/workloads/RefActivationWorkload.cpp | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/backends/reference/workloads/RefActivationWorkload.cpp b/src/backends/reference/workloads/RefActivationWorkload.cpp new file mode 100644 index 0000000000..78c971e183 --- /dev/null +++ b/src/backends/reference/workloads/RefActivationWorkload.cpp @@ -0,0 +1,33 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "RefActivationWorkload.hpp" + +#include "Activation.hpp" +#include "Decoders.hpp" +#include "Encoders.hpp" +#include "RefWorkloadUtils.hpp" + +#include "Profiling.hpp" + +namespace armnn +{ + +void RefActivationWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefActivationWorkload_Execute"); + + const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]); + const TensorInfo& outputInfo = GetTensorInfo(m_Data.m_Outputs[0]); + + Activation(*MakeDecoder<float>(inputInfo, m_Data.m_Inputs[0]->Map()), + *MakeEncoder<float>(outputInfo, m_Data.m_Outputs[0]->Map()), + inputInfo, + m_Data.m_Parameters.m_Function, + m_Data.m_Parameters.m_A, + m_Data.m_Parameters.m_B); +} + +} //namespace armnn |