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| author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2019-06-14 11:09:19 +0100 |
|---|---|---|
| committer | Teresa Charlin <teresa.charlinreyes@arm.com> | 2019-06-18 15:20:43 +0100 |
| commit | edeeb168c6d2612d5b934158bf18c35c843dfc3e (patch) | |
| tree | 49aa615311c9906dd1bf20694eb6f7b45cfc20fd /src/backends/reference/test/RefLayerTests.cpp | |
| parent | 0e406eed386a4ea015ec703c84a74ea775d88b99 (diff) | |
| download | armnn-edeeb168c6d2612d5b934158bf18c35c843dfc3e.tar.gz | |
IVGCVSW-3264 Add Unit Test for Dilated Convolution2d to armnn
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I60da1414ab41ea196cdebc27f0f014a502274fa8
Diffstat (limited to 'src/backends/reference/test/RefLayerTests.cpp')
| -rw-r--r-- | src/backends/reference/test/RefLayerTests.cpp | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/backends/reference/test/RefLayerTests.cpp b/src/backends/reference/test/RefLayerTests.cpp index cf4d9fd6f9..a45c248ce6 100644 --- a/src/backends/reference/test/RefLayerTests.cpp +++ b/src/backends/reference/test/RefLayerTests.cpp @@ -68,6 +68,56 @@ ARMNN_AUTO_TEST_CASE(SimpleConvolution2dAsymmetricPaddingNhwc, ARMNN_AUTO_TEST_CASE(SimpleConvolution2dSquareNhwc, SimpleConvolution2d3x3NhwcTest, false) +ARMNN_AUTO_TEST_CASE(Convolution2d3x3Dilation3x3, + Convolution2d3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>, + false, + armnn::DataLayout::NCHW) +ARMNN_AUTO_TEST_CASE(Convolution2d3x3Dilation3x3Nhwc, + Convolution2d3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>, + false, + armnn::DataLayout::NHWC) +ARMNN_AUTO_TEST_CASE(Convolution2d3x3Dilation3x3Uint8, + Convolution2d3x3Dilation3x3Test<armnn::DataType::QuantisedAsymm8, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NCHW) +ARMNN_AUTO_TEST_CASE(Convolution2d3x3Dilation3x3NhwcUint8, + Convolution2d3x3Dilation3x3Test<armnn::DataType::QuantisedAsymm8, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NHWC) +ARMNN_AUTO_TEST_CASE(Convolution2d3x3Dilation3x3Int16, + Convolution2d3x3Dilation3x3Test<armnn::DataType::QuantisedSymm16, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NCHW) +ARMNN_AUTO_TEST_CASE(Convolution2d3x3Dilation3x3NhwcInt16, + Convolution2d3x3Dilation3x3Test<armnn::DataType::QuantisedSymm16, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NHWC) + +ARMNN_AUTO_TEST_CASE(Convolution2d2x3x3Dilation3x3, + Convolution2d2x3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>, + false, + armnn::DataLayout::NCHW) +ARMNN_AUTO_TEST_CASE(Convolution2d2x3x3Dilation3x3Nhwc, + Convolution2d2x3x3Dilation3x3Test<armnn::DataType::Float32, armnn::DataType::Float32>, + false, + armnn::DataLayout::NHWC) +ARMNN_AUTO_TEST_CASE(Convolution2d2x3x3Dilation3x3Uint8, + Convolution2d2x3x3Dilation3x3Test<armnn::DataType::QuantisedAsymm8, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NCHW) +ARMNN_AUTO_TEST_CASE(Convolution2d2x3x3Dilation3x3NhwcUint8, + Convolution2d2x3x3Dilation3x3Test<armnn::DataType::QuantisedAsymm8, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NHWC) +ARMNN_AUTO_TEST_CASE(Convolution2d2x3x3Dilation3x3Int16, + Convolution2d2x3x3Dilation3x3Test<armnn::DataType::QuantisedSymm16, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NCHW) +ARMNN_AUTO_TEST_CASE(Convolution2d2x3x3Dilation3x3NhwcInt16, + Convolution2d2x3x3Dilation3x3Test<armnn::DataType::QuantisedSymm16, armnn::DataType::Signed32>, + false, + armnn::DataLayout::NHWC) + // Depthwise Convolution ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2d, DepthwiseConvolution2dTest, true, armnn::DataLayout::NCHW) ARMNN_AUTO_TEST_CASE(DepthwiseConvolution2dUint8, DepthwiseConvolution2dUint8Test, true, armnn::DataLayout::NCHW) |