diff options
author | James Conroy <james.conroy@arm.com> | 2019-09-17 14:22:06 +0100 |
---|---|---|
committer | Matteo Martincigh <matteo.martincigh@arm.com> | 2019-10-03 11:50:51 +0000 |
commit | d47a064ab4c38559c6be931cb1771feb6e026ea4 (patch) | |
tree | 5f2cad86258378e23e8c9d43a9555dcc2a443b7f /src/backends/neon/workloads | |
parent | 61d6f7305b02e025ee10aa07e5499993a0e77cc1 (diff) | |
download | armnn-d47a064ab4c38559c6be931cb1771feb6e026ea4.tar.gz |
IVGCVSW-3696 Add NEON ArgMinMax workload and tests
* Added layer tests and fixed WorkloadData validate.
* Also enabled copy to/from NEON for Signed32.
Signed-off-by: James Conroy <james.conroy@arm.com>
Change-Id: I5e961f88434e18d5a8ebff956d20a1c2cf1b50bb
Diffstat (limited to 'src/backends/neon/workloads')
-rw-r--r-- | src/backends/neon/workloads/CMakeLists.txt | 2 | ||||
-rw-r--r-- | src/backends/neon/workloads/NeonArgMinMaxWorkload.cpp | 79 | ||||
-rw-r--r-- | src/backends/neon/workloads/NeonArgMinMaxWorkload.hpp | 29 | ||||
-rw-r--r-- | src/backends/neon/workloads/NeonWorkloads.hpp | 1 |
4 files changed, 111 insertions, 0 deletions
diff --git a/src/backends/neon/workloads/CMakeLists.txt b/src/backends/neon/workloads/CMakeLists.txt index 42ac641369..f8d5922b70 100644 --- a/src/backends/neon/workloads/CMakeLists.txt +++ b/src/backends/neon/workloads/CMakeLists.txt @@ -10,6 +10,8 @@ list(APPEND armnnNeonBackendWorkloads_sources NeonActivationWorkload.hpp NeonAdditionWorkload.cpp NeonAdditionWorkload.hpp + NeonArgMinMaxWorkload.cpp + NeonArgMinMaxWorkload.hpp NeonBatchNormalizationWorkload.cpp NeonBatchNormalizationWorkload.hpp NeonConcatWorkload.cpp diff --git a/src/backends/neon/workloads/NeonArgMinMaxWorkload.cpp b/src/backends/neon/workloads/NeonArgMinMaxWorkload.cpp new file mode 100644 index 0000000000..e8d537f2ef --- /dev/null +++ b/src/backends/neon/workloads/NeonArgMinMaxWorkload.cpp @@ -0,0 +1,79 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "NeonArgMinMaxWorkload.hpp" +#include "NeonWorkloadUtils.hpp" + +#include <aclCommon/ArmComputeTensorUtils.hpp> +#include <backendsCommon/CpuTensorHandle.hpp> +#include <TensorUtils.hpp> + +#include <arm_compute/runtime/NEON/functions/NEArgMinMaxLayer.h> + +namespace +{ +unsigned int CalcAclAxis(unsigned int numDimensions, unsigned int axisIndex) +{ + return (numDimensions - axisIndex) - 1; +} + +} //namespace + +namespace armnn +{ + +arm_compute::Status NeonArgMinMaxWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const ArgMinMaxDescriptor& descriptor) +{ + const arm_compute::TensorInfo aclInput = armcomputetensorutils::BuildArmComputeTensorInfo(input); + const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output); + + auto numDims = input.GetNumDimensions(); + auto unsignedAxis = armnnUtils::GetUnsignedAxis(numDims, descriptor.m_Axis); + int aclAxis = boost::numeric_cast<int>(CalcAclAxis(numDims, unsignedAxis)); + + if (descriptor.m_Function == ArgMinMaxFunction::Max) + { + return arm_compute::NEArgMinMaxLayer::validate(&aclInput, aclAxis, &aclOutput, + arm_compute::ReductionOperation::ARG_IDX_MAX); + } + else + { + return arm_compute::NEArgMinMaxLayer::validate(&aclInput, aclAxis, &aclOutput, + arm_compute::ReductionOperation::ARG_IDX_MIN); + } +} + + +NeonArgMinMaxWorkload::NeonArgMinMaxWorkload(const ArgMinMaxQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<ArgMinMaxQueueDescriptor>(descriptor, info) +{ + arm_compute::ITensor& input = boost::polymorphic_downcast<IAclTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ITensor& output = boost::polymorphic_downcast<IAclTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + auto numDims = info.m_InputTensorInfos[0].GetNumDimensions(); + auto unsignedAxis = armnnUtils::GetUnsignedAxis(numDims, m_Data.m_Parameters.m_Axis); + int aclAxis = boost::numeric_cast<int>(CalcAclAxis(numDims, unsignedAxis)); + + if (m_Data.m_Parameters.m_Function == ArgMinMaxFunction::Max) + { + m_ArgMinMaxLayer.configure(&input, aclAxis, &output, arm_compute::ReductionOperation::ARG_IDX_MAX); + } + else + { + m_ArgMinMaxLayer.configure(&input, aclAxis, &output, arm_compute::ReductionOperation::ARG_IDX_MIN); + } +} + +void NeonArgMinMaxWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_NEON("NeonArgMinMaxWorkload_Execute"); + m_ArgMinMaxLayer.run(); +} + +} //namespace armnn + diff --git a/src/backends/neon/workloads/NeonArgMinMaxWorkload.hpp b/src/backends/neon/workloads/NeonArgMinMaxWorkload.hpp new file mode 100644 index 0000000000..6301b13718 --- /dev/null +++ b/src/backends/neon/workloads/NeonArgMinMaxWorkload.hpp @@ -0,0 +1,29 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include <backendsCommon/Workload.hpp> + +#include <arm_compute/core/Error.h> +#include <arm_compute/runtime/NEON/functions/NEArgMinMaxLayer.h> +namespace armnn +{ + +arm_compute::Status NeonArgMinMaxWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const ArgMinMaxDescriptor& descriptor); + +class NeonArgMinMaxWorkload : public BaseWorkload<ArgMinMaxQueueDescriptor> +{ +public: + NeonArgMinMaxWorkload(const ArgMinMaxQueueDescriptor& descriptor, const WorkloadInfo& info); + virtual void Execute() const override; + +private: + mutable arm_compute::NEArgMinMaxLayer m_ArgMinMaxLayer; +}; + +} //namespace armnn diff --git a/src/backends/neon/workloads/NeonWorkloads.hpp b/src/backends/neon/workloads/NeonWorkloads.hpp index 9d35ed42fe..8044a4f004 100644 --- a/src/backends/neon/workloads/NeonWorkloads.hpp +++ b/src/backends/neon/workloads/NeonWorkloads.hpp @@ -7,6 +7,7 @@ #include "NeonAbsWorkload.hpp" #include "NeonActivationWorkload.hpp" #include "NeonAdditionWorkload.hpp" +#include "NeonArgMinMaxWorkload.hpp" #include "NeonBatchNormalizationWorkload.hpp" #include "NeonConstantWorkload.hpp" #include "NeonConvertFp16ToFp32Workload.hpp" |