IVGCVSW-7625 GpuFsa Op: Add Resize/Scale operator

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I695ef452d004ed7b606020037cad681ef1fc80c3

5 files changed, 124 insertions, 0 deletions

diff --git a/src/backends/gpuFsa/layers/CMakeLists.txt b/src/backends/gpuFsa/layers/CMakeLists.txt
index 8ffa934561..9ea36b6f2c 100644
--- a/src/backends/gpuFsa/layers/CMakeLists.txt
+++ b/src/backends/gpuFsa/layers/CMakeLists.txt
@@ -16,6 +16,8 @@ list(APPEND armnnGpuFsaBackendLayers_sources
         GpuFsaElementwiseBinarySub.hpp
         GpuFsaPooling2d.cpp
         GpuFsaPooling2d.hpp
+        GpuFsaResize.cpp
+        GpuFsaResize.hpp
         UtilsGpuFsa.cpp
         UtilsGpuFsa.hpp
     )
diff --git a/src/backends/gpuFsa/layers/GpuFsaResize.cpp b/src/backends/gpuFsa/layers/GpuFsaResize.cpp
new file mode 100644
index 0000000000..b46b601bad
--- /dev/null
+++ b/src/backends/gpuFsa/layers/GpuFsaResize.cpp
@@ -0,0 +1,79 @@
+//
+// Copyright © 2024 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "GpuFsaResize.hpp"
+#include "UtilsGpuFsa.hpp"
+
+#include <aclCommon/ArmComputeTensorUtils.hpp>
+
+#include <arm_compute/dynamic_fusion/sketch/gpu/GpuWorkloadContext.h>
+#include <arm_compute/dynamic_fusion/sketch/gpu/GpuWorkloadSketch.h>
+#include <arm_compute/dynamic_fusion/sketch/gpu/operators/GpuResize.h>
+#include <arm_compute/dynamic_fusion/sketch/gpu/operators/GpuOutput.h>
+
+using namespace arm_compute::experimental::dynamic_fusion;
+using namespace armnn::armcomputetensorutils;
+
+namespace armnn
+{
+
+arm_compute::Status GpuFsaResizeValidate(const TensorInfo& input,
+                                         const ResizeDescriptor& descriptor)
+{
+    // Create a new workload sketch, for validation purposes
+    auto compileCtx         = arm_compute::CLKernelLibrary::get().get_compile_context();
+    auto workloadContext    = GpuWorkloadContext(&compileCtx);
+    GpuWorkloadSketch sketch{ &workloadContext };
+
+    arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
+    aclInputInfo.set_are_values_constant(input.IsConstant());
+    arm_compute::ITensorInfo* inputInfo = workloadContext.create_tensor_info(aclInputInfo);
+
+    ResizeAttributes resizeAttributes = CreateResizeAttributes(descriptor);
+
+    return GpuResize::validate_op(sketch, inputInfo, resizeAttributes);
+}
+
+void GpuFsaResizeCreateOp(GpuFsaPreCompiledBlob* blob,
+                          const TensorInfo& input,
+                          const ResizeDescriptor& descriptor)
+{
+    GpuWorkloadSketch* sketch           = blob->sketch.get();
+    GpuWorkloadContext* workloadContext = blob->workloadContext.get();
+    std::vector<arm_compute::ITensorInfo*> inputTensorInfos  = {};
+    std::vector<arm_compute::ITensorInfo*> outputTensorInfos = {};
+
+    arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input, descriptor.m_DataLayout);
+    aclInputInfo.set_are_values_constant(input.IsConstant());
+
+    inputTensorInfos.emplace_back(workloadContext->create_tensor_info(aclInputInfo));
+
+    ResizeAttributes resizeAttributes = CreateResizeAttributes(descriptor);
+
+    // Validate operator, check status and update reasonIfUnsupported
+    arm_compute::Status aclStatus = GpuResize::validate_op(*sketch,
+                                                           inputTensorInfos[0],
+                                                           resizeAttributes);
+
+    const bool supported = aclStatus.error_code() == arm_compute::ErrorCode::OK;
+    if (!supported)
+    {
+        throw BackendCapabilityException("\"GpuFsa\" backend failed during resize validation");
+    }
+
+    arm_compute::ITensorInfo* addOutputInfo = GpuResize::create_op(*sketch,
+                                                                   inputTensorInfos[0],
+                                                                   resizeAttributes);
+
+    // Temporary fix until fusing attempt is make for GpuFsa backend and Output layer workload is created.
+    outputTensorInfos.emplace_back(workloadContext->create_tensor_info());
+    GpuOutput::create_op(*sketch, addOutputInfo, outputTensorInfos[0]);
+
+    // Store the TensorInfos within the blob as unique_ptrs to be used later
+    blob->inputTensorInfos  = std::make_unique<std::vector<arm_compute::ITensorInfo*>>(inputTensorInfos);
+    blob->outputTensorInfos = std::make_unique<std::vector<arm_compute::ITensorInfo*>>(outputTensorInfos);
+}
+
+} // namespace armnn
\ No newline at end of file
diff --git a/src/backends/gpuFsa/layers/GpuFsaResize.hpp b/src/backends/gpuFsa/layers/GpuFsaResize.hpp
new file mode 100644
index 0000000000..04a2f77860
--- /dev/null
+++ b/src/backends/gpuFsa/layers/GpuFsaResize.hpp
@@ -0,0 +1,20 @@
+//
+// Copyright © 2024 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+#pragma once
+
+#include <armnn/Descriptors.hpp>
+
+#include <gpuFsa/GpuFsaBackend.hpp>
+
+namespace armnn
+{
+arm_compute::Status GpuFsaResizeValidate(const TensorInfo& input,
+                                         const ResizeDescriptor& descriptor);
+
+void GpuFsaResizeCreateOp(GpuFsaPreCompiledBlob* blob,
+                          const TensorInfo& input,
+                          const ResizeDescriptor& descriptor);
+
+} // namespace armnn
\ No newline at end of file
diff --git a/src/backends/gpuFsa/layers/UtilsGpuFsa.cpp b/src/backends/gpuFsa/layers/UtilsGpuFsa.cpp
index a1d96f0ec1..b11f91cc6c 100644
--- a/src/backends/gpuFsa/layers/UtilsGpuFsa.cpp
+++ b/src/backends/gpuFsa/layers/UtilsGpuFsa.cpp
@@ -58,4 +58,20 @@ CreatePool2dAttributes(const Pooling2dDescriptor& descriptor)
     pool2dAttributes.exclude_padding(excludePadding);
 
     return pool2dAttributes;
+}
+
+arm_compute::experimental::dynamic_fusion::ResizeAttributes
+CreateResizeAttributes(const armnn::ResizeDescriptor& descriptor)
+{
+    arm_compute::experimental::dynamic_fusion::ResizeAttributes resizeAttributes{};
+    resizeAttributes.output_width(static_cast<int32_t>(descriptor.m_TargetWidth));
+    resizeAttributes.output_height(static_cast<int32_t>(descriptor.m_TargetHeight));
+    resizeAttributes.interpolation_policy(descriptor.m_Method == ResizeMethod::Bilinear ?
+                                          arm_compute::InterpolationPolicy::BILINEAR :
+                                          arm_compute::InterpolationPolicy::NEAREST_NEIGHBOR);
+    resizeAttributes.sampling_policy(descriptor.m_HalfPixelCenters ? arm_compute::SamplingPolicy::CENTER
+                                                                   : arm_compute::SamplingPolicy::TOP_LEFT);
+    resizeAttributes.align_corners(descriptor.m_AlignCorners);
+
+    return resizeAttributes;
 }
\ No newline at end of file
diff --git a/src/backends/gpuFsa/layers/UtilsGpuFsa.hpp b/src/backends/gpuFsa/layers/UtilsGpuFsa.hpp
index 6c1d97ad87..2dbf363f93 100644
--- a/src/backends/gpuFsa/layers/UtilsGpuFsa.hpp
+++ b/src/backends/gpuFsa/layers/UtilsGpuFsa.hpp
@@ -9,6 +9,7 @@
 #include "arm_compute/dynamic_fusion/sketch/attributes/Conv2dAttributes.h"
 #include "arm_compute/dynamic_fusion/sketch/attributes/DepthwiseConv2dAttributes.h"
 #include "arm_compute/dynamic_fusion/sketch/attributes/Pool2dAttributes.h"
+#include "arm_compute/dynamic_fusion/sketch/attributes/ResizeAttributes.h"
 
 /// Utility function used to setup an arm_compute::Conv2dAttributes object from given descriptor
 /// @param[in] armnn::Convolution2dDescriptor
@@ -28,3 +29,9 @@ CreateDWConv2dAttributes(const armnn::DepthwiseConvolution2dDescriptor& descript
 /// @return arm_compute::experimental::dynamic_fusion::Pool2dAttributes
 arm_compute::experimental::dynamic_fusion::Pool2dAttributes
 CreatePool2dAttributes(const armnn::Pooling2dDescriptor& descriptor);
+
+/// Utility function used to setup an arm_compute::ResizeDescriptor object from given descriptor
+/// @param[in] armnn::ResizeDescriptor
+/// @return arm_compute::experimental::dynamic_fusion::ResizeAttributes
+arm_compute::experimental::dynamic_fusion::ResizeAttributes
+CreateResizeAttributes(const armnn::ResizeDescriptor& descriptor);