IVGCVSW-6088 Add Sin and Log to ElementWiseUnary

* Ref workload
* Cl workload
* Neon workload
* Serializer
* Deserializer

* Remove boost include from TensorTest.cpp

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I498548169cc77609c55cf3105f1de5a7429772cf

6 files changed, 158 insertions, 2 deletions

diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt
index 9f1a02f9bf..a351f73aa6 100644
--- a/src/backends/cl/workloads/CMakeLists.txt
+++ b/src/backends/cl/workloads/CMakeLists.txt
@@ -36,8 +36,8 @@ list(APPEND armnnClBackendWorkloads_sources
     ClDepthwiseConvolutionWorkload.hpp
     ClDequantizeWorkload.cpp
     ClDequantizeWorkload.hpp
-        ClDivisionWorkload.cpp
-        ClDivisionWorkload.hpp
+    ClDivisionWorkload.cpp
+    ClDivisionWorkload.hpp
     ClExpWorkload.cpp
     ClExpWorkload.hpp
     ClFillWorkload.cpp
@@ -50,6 +50,8 @@ list(APPEND armnnClBackendWorkloads_sources
     ClGatherWorkload.hpp
     ClInstanceNormalizationWorkload.cpp
     ClInstanceNormalizationWorkload.hpp
+    ClLogWorkload.cpp
+    ClLogWorkload.hpp
     ClL2NormalizationFloatWorkload.cpp
     ClL2NormalizationFloatWorkload.hpp
     ClLogicalAndWorkload.cpp
@@ -97,6 +99,8 @@ list(APPEND armnnClBackendWorkloads_sources
     ClResizeWorkload.hpp
     ClRsqrtWorkload.cpp
     ClRsqrtWorkload.hpp
+    ClSinWorkload.cpp
+    ClSinWorkload.hpp
     ClSliceWorkload.cpp
     ClSliceWorkload.hpp
     ClSoftmaxWorkload.cpp
diff --git a/src/backends/cl/workloads/ClLogWorkload.cpp b/src/backends/cl/workloads/ClLogWorkload.cpp
new file mode 100644
index 0000000000..b35345f1ce
--- /dev/null
+++ b/src/backends/cl/workloads/ClLogWorkload.cpp
@@ -0,0 +1,45 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "ClLogWorkload.hpp"
+
+#include "ClWorkloadUtils.hpp"
+
+#include <aclCommon/ArmComputeTensorUtils.hpp>
+#include <armnn/utility/PolymorphicDowncast.hpp>
+
+#include <cl/ClTensorHandle.hpp>
+
+namespace armnn
+{
+
+arm_compute::Status ClLogWorkloadValidate(const TensorInfo& input, const TensorInfo& output)
+{
+    const arm_compute::TensorInfo aclInput  = armcomputetensorutils::BuildArmComputeTensorInfo(input);
+    const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output);
+
+    return arm_compute::CLLogLayer::validate(&aclInput, &aclOutput);
+}
+
+ClLogWorkload::ClLogWorkload(const ElementwiseUnaryQueueDescriptor& descriptor,
+                             const WorkloadInfo& info,
+                             const arm_compute::CLCompileContext& clCompileContext)
+    : BaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info)
+{
+    m_Data.ValidateInputsOutputs("ClLogWorkload", 1, 1);
+
+    arm_compute::ICLTensor& input  = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
+    arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
+    m_LogLayer.configure(clCompileContext, &input, &output);
+}
+
+void ClLogWorkload::Execute() const
+{
+    ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogWorkload_Execute");
+    RunClFunction(m_LogLayer, CHECK_LOCATION());
+}
+
+} // namespace armnn
diff --git a/src/backends/cl/workloads/ClLogWorkload.hpp b/src/backends/cl/workloads/ClLogWorkload.hpp
new file mode 100644
index 0000000000..4339ab786d
--- /dev/null
+++ b/src/backends/cl/workloads/ClLogWorkload.hpp
@@ -0,0 +1,30 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+
+#include <arm_compute/core/Error.h>
+#include <arm_compute/runtime/CL/functions/CLElementWiseUnaryLayer.h>
+
+namespace armnn
+{
+
+arm_compute::Status ClLogWorkloadValidate(const TensorInfo& input, const TensorInfo& output);
+
+class ClLogWorkload : public BaseWorkload<ElementwiseUnaryQueueDescriptor>
+{
+public:
+    ClLogWorkload(const ElementwiseUnaryQueueDescriptor& descriptor,
+                  const WorkloadInfo& info,
+                  const arm_compute::CLCompileContext& clCompileContext);
+    virtual void Execute() const override;
+
+private:
+    mutable arm_compute::CLLogLayer m_LogLayer;
+};
+
+} // namespace armnn
diff --git a/src/backends/cl/workloads/ClSinWorkload.cpp b/src/backends/cl/workloads/ClSinWorkload.cpp
new file mode 100644
index 0000000000..17572c657b
--- /dev/null
+++ b/src/backends/cl/workloads/ClSinWorkload.cpp
@@ -0,0 +1,45 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "ClSinWorkload.hpp"
+
+#include "ClWorkloadUtils.hpp"
+
+#include <aclCommon/ArmComputeTensorUtils.hpp>
+#include <armnn/utility/PolymorphicDowncast.hpp>
+
+#include <cl/ClTensorHandle.hpp>
+
+namespace armnn
+{
+
+arm_compute::Status ClSinWorkloadValidate(const TensorInfo& input, const TensorInfo& output)
+{
+    const arm_compute::TensorInfo aclInput  = armcomputetensorutils::BuildArmComputeTensorInfo(input);
+    const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output);
+
+    return arm_compute::CLSinLayer::validate(&aclInput, &aclOutput);
+}
+
+ClSinWorkload::ClSinWorkload(const ElementwiseUnaryQueueDescriptor& descriptor,
+                             const WorkloadInfo& info,
+                             const arm_compute::CLCompileContext& clCompileContext)
+    : BaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info)
+{
+    m_Data.ValidateInputsOutputs("ClSinWorkload", 1, 1);
+
+    arm_compute::ICLTensor& input  = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
+    arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
+    m_SinLayer.configure(clCompileContext, &input, &output);
+}
+
+void ClSinWorkload::Execute() const
+{
+    ARMNN_SCOPED_PROFILING_EVENT_CL("ClSinWorkload_Execute");
+    RunClFunction(m_SinLayer, CHECK_LOCATION());
+}
+
+} // namespace armnn
diff --git a/src/backends/cl/workloads/ClSinWorkload.hpp b/src/backends/cl/workloads/ClSinWorkload.hpp
new file mode 100644
index 0000000000..5eb3b45476
--- /dev/null
+++ b/src/backends/cl/workloads/ClSinWorkload.hpp
@@ -0,0 +1,30 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+
+#include <arm_compute/core/Error.h>
+#include <arm_compute/runtime/CL/functions/CLElementWiseUnaryLayer.h>
+
+namespace armnn
+{
+
+arm_compute::Status ClSinWorkloadValidate(const TensorInfo& input, const TensorInfo& output);
+
+class ClSinWorkload : public BaseWorkload<ElementwiseUnaryQueueDescriptor>
+{
+public:
+    ClSinWorkload(const ElementwiseUnaryQueueDescriptor& descriptor,
+                  const WorkloadInfo& info,
+                  const arm_compute::CLCompileContext& clCompileContext);
+    virtual void Execute() const override;
+
+private:
+    mutable arm_compute::CLSinLayer m_SinLayer;
+};
+
+} // namespace armnn
diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp
index 5488fcdf1a..88d1c1ba93 100644
--- a/src/backends/cl/workloads/ClWorkloads.hpp
+++ b/src/backends/cl/workloads/ClWorkloads.hpp
@@ -25,6 +25,7 @@
 #include "ClGatherWorkload.hpp"
 #include "ClInstanceNormalizationWorkload.hpp"
 #include "ClL2NormalizationFloatWorkload.hpp"
+#include "ClLogWorkload.hpp"
 #include "ClLogicalAndWorkload.hpp"
 #include "ClLogicalNotWorkload.hpp"
 #include "ClLogicalOrWorkload.hpp"
@@ -49,6 +50,7 @@
 #include "ClReshapeWorkload.hpp"
 #include "ClResizeWorkload.hpp"
 #include "ClRsqrtWorkload.hpp"
+#include "ClSinWorkload.hpp"
 #include "ClSliceWorkload.hpp"
 #include "ClSoftmaxWorkload.hpp"
 #include "ClSpaceToBatchNdWorkload.hpp"