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author | Tianle Cheng <tianle.cheng@arm.com> | 2023-11-09 13:56:53 +0000 |
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committer | Tianle Cheng <tianle.cheng@arm.com> | 2023-11-10 17:39:25 +0000 |
commit | 21a9f33338c60ae1cd955df220ce329918adcb8f (patch) | |
tree | 0c684061fbfa88257bafa532eeab74cc06365350 /src/backends/cl/workloads | |
parent | 37acf49013ece8a3490174a4bfc1803e6f23b956 (diff) | |
download | armnn-21a9f33338c60ae1cd955df220ce329918adcb8f.tar.gz |
IVGCVSW-7835 Add ReverseV2 CL and Neon Workloads
* Added ReverseV2 to CL and Neon backends
* Added Cl and Neon ReverseV2 Layer unit tests
Signed-off-by: Tianle Cheng <tianle.cheng@arm.com>
Change-Id: I646275c629caf17dac1950b0cd7083f23f87f387
Diffstat (limited to 'src/backends/cl/workloads')
-rw-r--r-- | src/backends/cl/workloads/CMakeLists.txt | 2 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClReverseV2Workload.cpp | 50 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClReverseV2Workload.hpp | 33 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClWorkloads.hpp | 1 |
4 files changed, 86 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt index cb16ab19e8..f38366fa57 100644 --- a/src/backends/cl/workloads/CMakeLists.txt +++ b/src/backends/cl/workloads/CMakeLists.txt @@ -109,6 +109,8 @@ list(APPEND armnnClBackendWorkloads_sources ClReshapeWorkload.hpp ClResizeWorkload.cpp ClResizeWorkload.hpp + ClReverseV2Workload.cpp + ClReverseV2Workload.hpp ClRsqrtWorkload.cpp ClRsqrtWorkload.hpp ClSinWorkload.cpp diff --git a/src/backends/cl/workloads/ClReverseV2Workload.cpp b/src/backends/cl/workloads/ClReverseV2Workload.cpp new file mode 100644 index 0000000000..8802d33633 --- /dev/null +++ b/src/backends/cl/workloads/ClReverseV2Workload.cpp @@ -0,0 +1,50 @@ +// +// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClReverseV2Workload.hpp" +#include "ClWorkloadUtils.hpp" +#include <aclCommon/ArmComputeUtils.hpp> +#include <cl/ClTensorHandle.hpp> +#include <backendsCommon/WorkloadUtils.hpp> + +using namespace armnn::armcomputetensorutils; + +namespace armnn +{ +arm_compute::Status ClReverseV2WorkloadValidate(const TensorInfo& input, + const TensorInfo& axis, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInput = BuildArmComputeTensorInfo(input); + const arm_compute::TensorInfo aclAxis = BuildArmComputeTensorInfo(axis); + const arm_compute::TensorInfo aclOutput = BuildArmComputeTensorInfo(output); + + return arm_compute::CLReverse::validate(&aclInput, &aclOutput, &aclAxis, true); +} + +ClReverseV2Workload::ClReverseV2Workload(const armnn::ReverseV2QueueDescriptor &descriptor, + const armnn::WorkloadInfo &info, + const arm_compute::CLCompileContext& clCompileContext) + : BaseWorkload<ReverseV2QueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClReverseV2Workload", 2, 1); + + arm_compute::ICLTensor& input = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& axis = static_cast<IClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + { + ARMNN_SCOPED_PROFILING_EVENT_CL_NAME_GUID("ClReverseV2Workload_configure"); + m_Layer.configure(clCompileContext, &input, &output, &axis, true); + } +} + +void ClReverseV2Workload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL_NAME_GUID("ClReverseV2Workload_Execute"); + m_Layer.run(); +} + +} //namespace armnn
\ No newline at end of file diff --git a/src/backends/cl/workloads/ClReverseV2Workload.hpp b/src/backends/cl/workloads/ClReverseV2Workload.hpp new file mode 100644 index 0000000000..60d4a500e0 --- /dev/null +++ b/src/backends/cl/workloads/ClReverseV2Workload.hpp @@ -0,0 +1,33 @@ +// +// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include "ClBaseWorkload.hpp" + +#include <arm_compute/runtime/CL/functions/CLReverse.h> +#include <arm_compute/runtime/Tensor.h> +#include "arm_compute/runtime/CL/CLTensor.h" + +namespace armnn +{ +arm_compute::Status ClReverseV2WorkloadValidate(const TensorInfo& input, + const TensorInfo& axis, + const TensorInfo& output); + +class ClReverseV2Workload : public BaseWorkload<ReverseV2QueueDescriptor> +{ +public: + ClReverseV2Workload(const ReverseV2QueueDescriptor &descriptor, + const WorkloadInfo &info, + const arm_compute::CLCompileContext& clCompileContext); + + void Execute() const override; + +private: + mutable arm_compute::CLReverse m_Layer; +}; + +} //namespace armnn
\ No newline at end of file diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp index cec8706911..40b3e99258 100644 --- a/src/backends/cl/workloads/ClWorkloads.hpp +++ b/src/backends/cl/workloads/ClWorkloads.hpp @@ -55,6 +55,7 @@ #include "ClReduceWorkload.hpp" #include "ClReshapeWorkload.hpp" #include "ClResizeWorkload.hpp" +#include "ClReverseV2Workload.hpp" #include "ClRsqrtWorkload.hpp" #include "ClSinWorkload.hpp" #include "ClSliceWorkload.hpp" |