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author | Cian McGriskin <cian.mcgriskin@arm.com> | 2023-07-26 11:52:47 +0100 |
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committer | Nikhil Raj <nikhil.raj@arm.com> | 2023-08-04 20:48:03 +0100 |
commit | 3b3dcbf0321fadcb2b7b5b550a4d03f510d7cb7b (patch) | |
tree | 9658a4d20fc73bfb8498aa8617202c49406f9eaa /src/backends/cl/workloads | |
parent | 88bef3acd73069df13256e818f32555b19e1a8b4 (diff) | |
download | armnn-3b3dcbf0321fadcb2b7b5b550a4d03f510d7cb7b.tar.gz |
IVGCVSW-2291 TILE Operator CL Implementation
* Added Tile Operator Implementation to CL
* Added calls to the existing UnitTests
* Added Documentation
Signed-off-by: Cian McGriskin <cian.mcgriskin@arm.com>
Change-Id: If7d25c7aa669c24e7816e5d445c7a3b9ce6972d4
Diffstat (limited to 'src/backends/cl/workloads')
-rw-r--r-- | src/backends/cl/workloads/CMakeLists.txt | 2 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClTileWorkload.cpp | 50 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClTileWorkload.hpp | 27 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClWorkloads.hpp | 1 |
4 files changed, 80 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt index 030d71988f..cb16ab19e8 100644 --- a/src/backends/cl/workloads/CMakeLists.txt +++ b/src/backends/cl/workloads/CMakeLists.txt @@ -131,6 +131,8 @@ list(APPEND armnnClBackendWorkloads_sources ClStridedSliceWorkload.hpp ClSubtractionWorkload.cpp ClSubtractionWorkload.hpp + ClTileWorkload.cpp + ClTileWorkload.hpp ClTransposeConvolution2dWorkload.cpp ClTransposeConvolution2dWorkload.hpp ClTransposeWorkload.cpp diff --git a/src/backends/cl/workloads/ClTileWorkload.cpp b/src/backends/cl/workloads/ClTileWorkload.cpp new file mode 100644 index 0000000000..2c2f63faac --- /dev/null +++ b/src/backends/cl/workloads/ClTileWorkload.cpp @@ -0,0 +1,50 @@ +// +// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClTileWorkload.hpp" +#include "ClWorkloadUtils.hpp" +#include <aclCommon/ArmComputeUtils.hpp> +#include <cl/ClTensorHandle.hpp> +#include <vector> +#include <algorithm> + +using namespace armnn::armcomputetensorutils; +namespace armnn +{ +arm_compute::Status ClTileWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const TileDescriptor& descriptor) +{ + const arm_compute::TensorInfo aclInput = BuildArmComputeTensorInfo(input); + const arm_compute::TensorInfo aclOutput = BuildArmComputeTensorInfo(output); + + std::vector<uint32_t> aclMultiples = descriptor.m_Multiples; + std::reverse(aclMultiples.begin(),aclMultiples.end()); + + return arm_compute::CLTile::validate(&aclInput, &aclOutput, aclMultiples); +} + +ClTileWorkload::ClTileWorkload(const armnn::TileQueueDescriptor& descriptor, + const armnn::WorkloadInfo& info, + const arm_compute::CLCompileContext& clCompileContext) + : BaseWorkload<TileQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClTileWorkload", 1, 1); + + std::vector<uint32_t> aclMultiples = descriptor.m_Parameters.m_Multiples; + std::reverse(aclMultiples.begin(),aclMultiples.end()); + + arm_compute::ICLTensor& input = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + m_Layer.configure(clCompileContext, &input, &output, aclMultiples); +} + +void ClTileWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL_GUID("ClTileWorkload_Execute", this->GetGuid()); + m_Layer.run(); +} + +} //namespace armnn
\ No newline at end of file diff --git a/src/backends/cl/workloads/ClTileWorkload.hpp b/src/backends/cl/workloads/ClTileWorkload.hpp new file mode 100644 index 0000000000..0f68559f85 --- /dev/null +++ b/src/backends/cl/workloads/ClTileWorkload.hpp @@ -0,0 +1,27 @@ +// +// Copyright © 2023 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once +#include "ClBaseWorkload.hpp" +#include <arm_compute/runtime/CL/functions/CLTile.h> + +namespace armnn +{ +arm_compute::Status ClTileWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const TileDescriptor& descriptor); + +class ClTileWorkload : public BaseWorkload<TileQueueDescriptor> { +public: + ClTileWorkload(const TileQueueDescriptor &descriptor, + const WorkloadInfo &info, + const arm_compute::CLCompileContext& clCompileContext); + void Execute() const override; + +private: + mutable arm_compute::CLTile m_Layer; +}; + +} //namespace armnn
\ No newline at end of file diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp index d862aab949..cec8706911 100644 --- a/src/backends/cl/workloads/ClWorkloads.hpp +++ b/src/backends/cl/workloads/ClWorkloads.hpp @@ -68,6 +68,7 @@ #include "ClSubtractionWorkload.hpp" #include "ClConvertFp16ToFp32Workload.hpp" #include "ClConvertFp32ToFp16Workload.hpp" +#include "ClTileWorkload.hpp" #include "ClTransposeConvolution2dWorkload.hpp" #include "ClTransposeWorkload.hpp" #include "ClUnidirectionalSequenceLstmFloatWorkload.hpp" |