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author | James Conroy <james.conroy@arm.com> | 2019-09-19 17:00:31 +0100 |
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committer | James Conroy <james.conroy@arm.com> | 2019-11-13 12:17:48 +0000 |
commit | 2dc0572f4d9f28b2e0c38b8ff183b3f7bd9900da (patch) | |
tree | 206e34307dd62cfdfe8d1677f3e238658119b1e0 /src/backends/cl/workloads | |
parent | 663c1849b2c359e6d898a763fff2ef013b55a459 (diff) | |
download | armnn-2dc0572f4d9f28b2e0c38b8ff183b3f7bd9900da.tar.gz |
IVGCVSW-3695 Add CL ArgMinMax workload
* Also enabled copy to/from CL for Signed32.
Signed-off-by: James Conroy <james.conroy@arm.com>
Change-Id: I0113182891f9767de73f04dcd81252c84c996eda
Diffstat (limited to 'src/backends/cl/workloads')
-rw-r--r-- | src/backends/cl/workloads/CMakeLists.txt | 2 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClArgMinMaxWorkload.cpp | 82 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClArgMinMaxWorkload.hpp | 30 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClWorkloads.hpp | 1 |
4 files changed, 115 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt index a9f320d51f..94c4a3e967 100644 --- a/src/backends/cl/workloads/CMakeLists.txt +++ b/src/backends/cl/workloads/CMakeLists.txt @@ -10,6 +10,8 @@ list(APPEND armnnClBackendWorkloads_sources ClActivationWorkload.hpp ClAdditionWorkload.cpp ClAdditionWorkload.hpp + ClArgMinMaxWorkload.cpp + ClArgMinMaxWorkload.hpp ClBatchNormalizationFloatWorkload.cpp ClBatchNormalizationFloatWorkload.hpp ClBatchToSpaceNdWorkload.cpp diff --git a/src/backends/cl/workloads/ClArgMinMaxWorkload.cpp b/src/backends/cl/workloads/ClArgMinMaxWorkload.cpp new file mode 100644 index 0000000000..3270b0a2f3 --- /dev/null +++ b/src/backends/cl/workloads/ClArgMinMaxWorkload.cpp @@ -0,0 +1,82 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClArgMinMaxWorkload.hpp" +#include "ClWorkloadUtils.hpp" + +#include <aclCommon/ArmComputeTensorUtils.hpp> + +#include <backendsCommon/CpuTensorHandle.hpp> + +#include <TensorUtils.hpp> + +#include <cl/ClTensorHandle.hpp> +#include <cl/ClLayerSupport.hpp> + +namespace +{ +unsigned int CalcAclAxis(unsigned int numDimensions, unsigned int axisIndex) +{ + return (numDimensions - axisIndex) - 1; +} + +} //namespace + +namespace armnn +{ + +arm_compute::Status ClArgMinMaxWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const ArgMinMaxDescriptor& descriptor) +{ + const arm_compute::TensorInfo aclInput = armcomputetensorutils::BuildArmComputeTensorInfo(input); + const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output); + + auto numDims = input.GetNumDimensions(); + auto unsignedAxis = armnnUtils::GetUnsignedAxis(numDims, descriptor.m_Axis); + int aclAxis = boost::numeric_cast<int>(CalcAclAxis(numDims, unsignedAxis)); + + if (descriptor.m_Function == ArgMinMaxFunction::Max) + { + return arm_compute::CLArgMinMaxLayer::validate(&aclInput, aclAxis, &aclOutput, + arm_compute::ReductionOperation::ARG_IDX_MAX); + } + else + { + return arm_compute::CLArgMinMaxLayer::validate(&aclInput, aclAxis, &aclOutput, + arm_compute::ReductionOperation::ARG_IDX_MIN); + } +} + + +ClArgMinMaxWorkload::ClArgMinMaxWorkload(const ArgMinMaxQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<ArgMinMaxQueueDescriptor>(descriptor, info) +{ + arm_compute::ICLTensor& input = static_cast<IClTensorHandle*>(this->m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(this->m_Data.m_Outputs[0])->GetTensor(); + + auto numDims = info.m_InputTensorInfos[0].GetNumDimensions(); + auto unsignedAxis = armnnUtils::GetUnsignedAxis(numDims, m_Data.m_Parameters.m_Axis); + int aclAxis = boost::numeric_cast<int>(CalcAclAxis(numDims, unsignedAxis)); + + if (m_Data.m_Parameters.m_Function == ArgMinMaxFunction::Max) + { + m_ArgMinMaxLayer.configure(&input, aclAxis, &output, arm_compute::ReductionOperation::ARG_IDX_MAX); + } + else + { + m_ArgMinMaxLayer.configure(&input, aclAxis, &output, arm_compute::ReductionOperation::ARG_IDX_MIN); + } +} + +void ClArgMinMaxWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClArgMinMaxWorkload_Execute"); + RunClFunction(m_ArgMinMaxLayer, CHECK_LOCATION()); +} + +} //namespace armnn + diff --git a/src/backends/cl/workloads/ClArgMinMaxWorkload.hpp b/src/backends/cl/workloads/ClArgMinMaxWorkload.hpp new file mode 100644 index 0000000000..54f28e6175 --- /dev/null +++ b/src/backends/cl/workloads/ClArgMinMaxWorkload.hpp @@ -0,0 +1,30 @@ +// +// Copyright © 2019 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include <backendsCommon/Workload.hpp> + +#include <arm_compute/core/Error.h> +#include <arm_compute/runtime/CL/functions/CLArgMinMaxLayer.h> + +namespace armnn +{ + +arm_compute::Status ClArgMinMaxWorkloadValidate(const TensorInfo& input, + const TensorInfo& output, + const ArgMinMaxDescriptor& descriptor); + +class ClArgMinMaxWorkload : public BaseWorkload<ArgMinMaxQueueDescriptor> +{ +public: + ClArgMinMaxWorkload(const ArgMinMaxQueueDescriptor& descriptor, const WorkloadInfo& info); + virtual void Execute() const override; + +private: + mutable arm_compute::CLArgMinMaxLayer m_ArgMinMaxLayer; +}; + +} //namespace armnn diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp index cd6ca5fe17..dd8c6996d4 100644 --- a/src/backends/cl/workloads/ClWorkloads.hpp +++ b/src/backends/cl/workloads/ClWorkloads.hpp @@ -7,6 +7,7 @@ #include "ClAbsWorkload.hpp" #include "ClActivationWorkload.hpp" #include "ClAdditionWorkload.hpp" +#include "ClArgMinMaxWorkload.hpp" #include "ClConstantWorkload.hpp" #include "ClBatchNormalizationFloatWorkload.hpp" #include "ClBatchToSpaceNdWorkload.hpp" |