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| author | josh minor <josh.minor@arm.com> | 2019-11-13 10:55:17 -0600 |
|---|---|---|
| committer | Matteo Martincigh <matteo.martincigh@arm.com> | 2019-11-19 14:45:53 +0000 |
| commit | ba424d2aff70a13e1a16c4f9018a0bea4e5c11b3 (patch) | |
| tree | 35c3c0823764888341686110405dabba35a2a426 /src/backends/cl/workloads/ClPooling2dWorkload.cpp | |
| parent | 52ec3463086a12282d8b833521e9e32d1055c6a6 (diff) | |
| download | armnn-ba424d2aff70a13e1a16c4f9018a0bea4e5c11b3.tar.gz | |
IVGCVSW-1530 Add TfLite slice parser and fix transpose perm vector creation
* TfLite slice parser and relevant tests added
* TfLite transpose parser logic added to translate Tf/np permutation
vector definitions to Armnn definitions
* TfLite transpose parser no permute data test modified to include
data for default permutation vector when none specified
Signed-off-by: josh minor <josh.minor@arm.com>
Change-Id: Iebd30971bd180593dc6b8f0d5be1d1bc61a3a5bf
Diffstat (limited to 'src/backends/cl/workloads/ClPooling2dWorkload.cpp')
0 files changed, 0 insertions, 0 deletions