IVGCVSW-2972 Support QSymm16 for Merger

Change-Id: If2289b2d1fc20f4524fcf4620f01ea3a36d727d2
Signed-off-by: Jim Flynn <jim.flynn@arm.com>

1 files changed, 21 insertions, 0 deletions

diff --git a/src/backends/backendsCommon/WorkloadData.cpp b/src/backends/backendsCommon/WorkloadData.cpp
index 58f77d55c5..335e7c5fcd 100644
--- a/src/backends/backendsCommon/WorkloadData.cpp
+++ b/src/backends/backendsCommon/WorkloadData.cpp
@@ -445,6 +445,27 @@ void MergerQueueDescriptor::Validate(const WorkloadInfo& workloadInfo) const
             }
         }
     }
+
+    // Check the supported data types
+    std::vector<DataType> supportedTypes =
+    {
+            DataType::Float32,
+            DataType::Float16,
+            DataType::Boolean,
+            DataType::Signed32,
+            DataType::QuantisedAsymm8,
+            DataType::QuantisedSymm16
+    };
+
+    for (unsigned long i = 0; i < workloadInfo.m_InputTensorInfos.size(); ++i)
+    {
+        ValidateDataTypes(workloadInfo.m_InputTensorInfos[i],
+                          supportedTypes,
+                          "MergerQueueDescriptor");
+    }
+    ValidateDataTypes(workloadInfo.m_OutputTensorInfos[0],
+                      {workloadInfo.m_InputTensorInfos[0].GetDataType()},
+                      "MergerQueueDescriptor");
 }
 
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