GitHub #640 Add support for CEIL operator

* Reference workload
* TfLite Delegate
* TfLite Parser
* Serializer and Deserializer
* Changed fallback tests in delegate to use COS instead of CEIL

Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: I36e0dbff33694182d1dba0c95d463506428e2f04

3 files changed, 19 insertions, 1 deletions

diff --git a/src/armnnTfLiteParser/TfLiteParser.cpp b/src/armnnTfLiteParser/TfLiteParser.cpp
index ee4cadd216..2a7f049470 100644
--- a/src/armnnTfLiteParser/TfLiteParser.cpp
+++ b/src/armnnTfLiteParser/TfLiteParser.cpp
@@ -729,6 +729,7 @@ TfLiteParserImpl::TfLiteParserImpl(const Optional<ITfLiteParser::TfLiteParserOpt
     m_ParserFunctions[tflite::BuiltinOperator_AVERAGE_POOL_2D]         = &TfLiteParserImpl::ParseAveragePool2D;
     m_ParserFunctions[tflite::BuiltinOperator_BATCH_TO_SPACE_ND]       = &TfLiteParserImpl::ParseBatchToSpaceND;
     m_ParserFunctions[tflite::BuiltinOperator_BATCH_MATMUL]            = &TfLiteParserImpl::ParseBatchMatMul;
+    m_ParserFunctions[tflite::BuiltinOperator_CEIL]                    = &TfLiteParserImpl::ParseCeil;
     m_ParserFunctions[tflite::BuiltinOperator_CAST]                    = &TfLiteParserImpl::ParseCast;
     m_ParserFunctions[tflite::BuiltinOperator_CONCATENATION]           = &TfLiteParserImpl::ParseConcatenation;
     m_ParserFunctions[tflite::BuiltinOperator_CONV_2D]                 = &TfLiteParserImpl::ParseConv2D;
@@ -4509,6 +4510,11 @@ void TfLiteParserImpl::ParseAbs(size_t subgraphIndex, size_t operatorIndex)
     ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Abs);
 }
 
+void TfLiteParserImpl::ParseCeil(size_t subgraphIndex, size_t operatorIndex)
+{
+    ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Ceil);
+}
+
 void TfLiteParserImpl::ParseExp(size_t subgraphIndex, size_t operatorIndex)
 {
     ParseElementwiseUnary(subgraphIndex, operatorIndex, armnn::UnaryOperation::Exp);
diff --git a/src/armnnTfLiteParser/TfLiteParser.hpp b/src/armnnTfLiteParser/TfLiteParser.hpp
index ec03c23a54..91fad43b8a 100644
--- a/src/armnnTfLiteParser/TfLiteParser.hpp
+++ b/src/armnnTfLiteParser/TfLiteParser.hpp
@@ -118,6 +118,7 @@ private:
     void ParseBatchMatMul(size_t subgraphIndex, size_t operatorIndex);
     void ParseBatchToSpaceND(size_t subgraphIndex, size_t operatorIndex);
     void ParseCast(size_t subgraphIndex, size_t operatorIndex);
+    void ParseCeil(size_t subgraphIndex, size_t operatorIndex);
     void ParseComparison(size_t subgraphIndex, size_t operatorIndex, armnn::ComparisonOperation comparisonOperation);
     void ParseConcatenation(size_t subgraphIndex, size_t operatorIndex);
     void ParseConv2D(size_t subgraphIndex, size_t operatorIndex);
diff --git a/src/armnnTfLiteParser/test/ElementWiseUnary.cpp b/src/armnnTfLiteParser/test/ElementWiseUnary.cpp
index 67c2080d60..ffdf1cca61 100644
--- a/src/armnnTfLiteParser/test/ElementWiseUnary.cpp
+++ b/src/armnnTfLiteParser/test/ElementWiseUnary.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
+// Copyright © 2021-2023 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -180,4 +180,15 @@ TEST_CASE_FIXTURE(SimpleSinFixture, "ParseSin")
                                                              0.4794255386f, -0.99177885344f, -0.8414709848f} }});
 }
 
+struct SimpleCeilFixture : public ElementWiseUnaryFixture
+{
+    SimpleCeilFixture() : ElementWiseUnaryFixture("CEIL", "FLOAT32", "[ 1, 2, 3, 1 ]", "[ 1, 2, 3, 1 ]") {}
+};
+
+TEST_CASE_FIXTURE(SimpleCeilFixture, "ParseCeil")
+{
+    RunTest<4, armnn::DataType::Float32>(0, {{ "inputTensor", { -50.5f, -25.9999f, -0.5f, 0.0f, 1.5555f, 25.5f } }},
+                                            {{ "outputTensor",{ -50.0f, -25.0f, 0.0f, 0.0f, 2.0f, 26.0f} }});
+}
+
 }