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author | Sadik Armagan <sadik.armagan@arm.com> | 2021-11-24 15:47:28 +0000 |
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committer | Sadik Armagan <sadik.armagan@arm.com> | 2021-12-14 11:02:41 +0000 |
commit | a097d2a0ed8e30d5aaf6d29ec18d0c39201b7b67 (patch) | |
tree | 947e587bc42d07f52c55b155308b5ea5bd3ebacd /src/armnnTestUtils/WorkloadTestUtils.hpp | |
parent | bc14881a76699dd942e94265116da68a6466455e (diff) | |
download | armnn-a097d2a0ed8e30d5aaf6d29ec18d0c39201b7b67.tar.gz |
IVGCVSW-6453 'Move the ArmNN Test Utils code to a physically separate directory'
* Created include/armnnTestUtils directory
* Moved Arm NN test utils files into armnnTestUtils directory
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
Change-Id: I03ac54c645c41c52650c4c03b6a58fb1481fef5d
Diffstat (limited to 'src/armnnTestUtils/WorkloadTestUtils.hpp')
-rw-r--r-- | src/armnnTestUtils/WorkloadTestUtils.hpp | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/src/armnnTestUtils/WorkloadTestUtils.hpp b/src/armnnTestUtils/WorkloadTestUtils.hpp new file mode 100644 index 0000000000..856e54a72a --- /dev/null +++ b/src/armnnTestUtils/WorkloadTestUtils.hpp @@ -0,0 +1,113 @@ +// +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// +#pragma once + +#include <armnn/Tensor.hpp> + +#include <armnn/backends/IBackendInternal.hpp> +#include <armnn/backends/IMemoryManager.hpp> +#include <backendsCommon/Workload.hpp> +#include <backendsCommon/WorkloadInfo.hpp> + +namespace armnn +{ +class ITensorHandle; +} // namespace armnn + +namespace +{ + +template <typename QueueDescriptor> +void AddInputToWorkload(QueueDescriptor& descriptor, + armnn::WorkloadInfo& info, + const armnn::TensorInfo& tensorInfo, + armnn::ITensorHandle* tensorHandle) +{ + descriptor.m_Inputs.push_back(tensorHandle); + info.m_InputTensorInfos.push_back(tensorInfo); +} + +template <typename QueueDescriptor> +void AddOutputToWorkload(QueueDescriptor& descriptor, + armnn::WorkloadInfo& info, + const armnn::TensorInfo& tensorInfo, + armnn::ITensorHandle* tensorHandle) +{ + descriptor.m_Outputs.push_back(tensorHandle); + info.m_OutputTensorInfos.push_back(tensorInfo); +} + +template <typename QueueDescriptor> +void SetWorkloadInput(QueueDescriptor& descriptor, + armnn::WorkloadInfo& info, + unsigned int index, + const armnn::TensorInfo& tensorInfo, + armnn::ITensorHandle* tensorHandle) +{ + descriptor.m_Inputs[index] = tensorHandle; + info.m_InputTensorInfos[index] = tensorInfo; +} + +template <typename QueueDescriptor> +void SetWorkloadOutput(QueueDescriptor& descriptor, + armnn::WorkloadInfo& info, + unsigned int index, + const armnn::TensorInfo& tensorInfo, + armnn::ITensorHandle* tensorHandle) +{ + descriptor.m_Outputs[index] = tensorHandle; + info.m_OutputTensorInfos[index] = tensorInfo; +} + +inline void ExecuteWorkload(armnn::IWorkload& workload, + const armnn::IBackendInternal::IMemoryManagerSharedPtr& memoryManager, + bool memoryManagementRequested = true) +{ + const bool manageMemory = memoryManager && memoryManagementRequested; + + // Acquire working memory (if needed) + if (manageMemory) + { + memoryManager->Acquire(); + } + + // Perform PostAllocationConfiguration + workload.PostAllocationConfigure(); + + // Execute the workload + workload.Execute(); + + // Release working memory (if needed) + if (manageMemory) + { + memoryManager->Release(); + } +} + +inline armnn::Optional<armnn::DataType> GetBiasTypeFromWeightsType(armnn::Optional<armnn::DataType> weightsType) +{ + if (!weightsType) + { + return weightsType; + } + + switch(weightsType.value()) + { + case armnn::DataType::BFloat16: + case armnn::DataType::Float16: + case armnn::DataType::Float32: + return weightsType; + case armnn::DataType::QAsymmS8: + case armnn::DataType::QAsymmU8: + case armnn::DataType::QSymmS8: + case armnn::DataType::QSymmS16: + return armnn::DataType::Signed32; + default: + ARMNN_ASSERT_MSG(false, "GetBiasTypeFromWeightsType(): Unsupported data type."); + } + return armnn::EmptyOptional(); +} + +} // anonymous namespace |