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author | Francis Murtagh <francis.murtagh@arm.com> | 2018-08-29 12:42:10 +0100 |
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committer | Matthew Bentham <matthew.bentham@arm.com> | 2018-09-17 17:21:23 +0100 |
commit | e7a86a4a3363993fb41b1ea62f23b3643b8b0c78 (patch) | |
tree | 6d054cae92a13412129525e4f9ea441e7d8c6b73 /src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp | |
parent | a68241066c3e797dab70f515d2c55aaa74abf564 (diff) | |
download | armnn-e7a86a4a3363993fb41b1ea62f23b3643b8b0c78.tar.gz |
IVGCVSW-1200 Division layer
*IVGCVSW-1772 Create QueueDescriptors
*IVGCVSW-1773 Add a CL implementation of the DivisionWorkload
*IVGCVSW-1774 Add Neon implementation of the DivisionWorkload
*IVGCVSW-1775 Add a Ref implementation of the DivisionWorkload
*IVGCVSW-1776 Add a Division Layer
* Added simple division unit tests with broadcasting
Change-Id: I05751fb7f868789f6c06f91e8d25e52b4f12ab5e
Diffstat (limited to 'src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp')
-rw-r--r-- | src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp b/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp new file mode 100644 index 0000000000..07345c345c --- /dev/null +++ b/src/armnn/backends/ClWorkloads/ClDivisionFloatWorkload.cpp @@ -0,0 +1,49 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "ClDivisionFloatWorkload.hpp" +#include "backends/ClTensorHandle.hpp" +#include "backends/CpuTensorHandle.hpp" + +namespace armnn +{ + +arm_compute::Status ClDivisionWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInput1 = armcomputetensorutils::BuildArmComputeTensorInfo(input0); + const arm_compute::TensorInfo aclInput2 = armcomputetensorutils::BuildArmComputeTensorInfo(input1); + const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output); + + // At the time of writing, configure() will fail if a rounding policy other than TO_ZERO is supplied to it, + // when providing a scale of 1.0 for F32 tensors, even though the provided rounding policy appears to be + // ignored for F32 tensors. + return arm_compute::CLArithmeticDivision::validate(&aclInput1, &aclInput2, &aclOutput); +} + + +ClDivisionFloatWorkload::ClDivisionFloatWorkload(const DivisionQueueDescriptor& descriptor, + const WorkloadInfo& info) + : FloatWorkload<DivisionQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClDivisionFloatWorkload", 2, 1); + + arm_compute::ICLTensor& input0 = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& input1 = static_cast<IClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + // Construct + m_ArithmeticDivision.configure(&input0, &input1, &output); +} + +void ClDivisionFloatWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClDivisionFloatWorkload_Execute"); + + // Executes the layer. + m_ArithmeticDivision.run(); +} + +} //namespace armnn |