From 3c673949b4ed3ab3129859b18439ed8fe87a6ad1 Mon Sep 17 00:00:00 2001 From: Mike Kelly Date: Thu, 25 Jul 2019 09:26:06 +0100 Subject: IVGCVSW-3521 CpuAcc V1.2 pad Failures * Fixed Pad and PadV2 failures and skips. * Templated ConvertPad to enable float16 tests to run. Signed-off-by: Mike Kelly Change-Id: I50ded84fe44ea5d5949e877f383f32adff88680d --- 1.2/HalPolicy.cpp | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to '1.2') diff --git a/1.2/HalPolicy.cpp b/1.2/HalPolicy.cpp index 906d6bcf..307475a8 100644 --- a/1.2/HalPolicy.cpp +++ b/1.2/HalPolicy.cpp @@ -68,7 +68,6 @@ bool HandledByV1_1(V1_2::OperationType operationType) case V1_1::OperationType::BATCH_TO_SPACE_ND: case V1_1::OperationType::DIV: case V1_1::OperationType::MEAN: - case V1_1::OperationType::PAD: case V1_1::OperationType::SPACE_TO_BATCH_ND: case V1_1::OperationType::SQUEEZE: case V1_1::OperationType::STRIDED_SLICE: @@ -146,6 +145,8 @@ bool HalPolicy::ConvertOperation(const Operation& operation, const Model& model, return ConvertMaximum(operation, model, data); case V1_2::OperationType::MINIMUM: return ConvertMinimum(operation, model, data); + case V1_2::OperationType::PAD: + return ConvertPad(operation, model, data); case V1_2::OperationType::PAD_V2: return ConvertPadV2(operation, model, data); case V1_2::OperationType::PRELU: @@ -675,15 +676,12 @@ bool HalPolicy::ConvertPadV2(const Operation& operation, const Model& model, Con } else if (operandType0 == OperandType::TENSOR_QUANT8_ASYMM && operandType2 == OperandType::INT32) { - int32_t quantizedPadValue = 0; - if (!GetInputInt32(operation, 2, quantizedPadValue, model, data)) + int32_t intPadValue = 0; + if (!GetInputInt32(operation, 2, intPadValue, model, data)) { return Fail("%s: Could not read input 2 (INT32)", __func__); } - - descriptor.m_PadValue = armnn::Dequantize(quantizedPadValue, - inputInfo.GetQuantizationScale(), - inputInfo.GetQuantizationOffset()); + descriptor.m_PadValue = intPadValue; } else { -- cgit v1.2.1