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/*
* Copyright (c) 2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef ARM_COMPUTE_CL_DIRECT_CONV2D_H
#define ARM_COMPUTE_CL_DIRECT_CONV2D_H
#include "arm_compute/function_info/ActivationLayerInfo.h"
#include "src/gpu/cl/ClCompileContext.h"
#include "src/gpu/cl/IClKernel.h"
#include "src/gpu/cl/IClOperator.h"
#include <memory>
namespace arm_compute
{
namespace opencl
{
/** Basic function to simulate a directly convolution layer. This function calls the following OpenCL kernels:
*
* -# @ref CLFillBorderKernel (executed if padding size is different from zero)
* -# @ref opencl::ClDirectConv2d
*/
class ClDirectConv2d : public IClOperator
{
public:
ClDirectConv2d() = default;
/** Set the src and dst tensors.
*
* @param[in] compile_context The compile context to be used.
* @param[in] src Source tensor. 3 lower dimensions represent a single src [width, height, IFM],
* while every optional dimension from 4 and above represent a batch of srcs.
* Data types supported: QASYMM8_SIGNED/QASYMM8/F16/F32.
* @param[in] weights Weights tensor. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. Data type supported:Same as @p src.
* @param[in] biases Biases tensor. Shared biases supported. Biases are 1D tensor with dimensions [OFM].
* Data type supported: Should match @p src data type, except for src of QASYMM8 and QASYMM8_SIGNED type where biases should be of S32 type.
* @param[out] dst Destination tensor. 3 lower dimensions represent a single dst [width, height, OFM], while the rest represent batch of dsts.
* Data types supported: Same as @p src.
* @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo.
* @param[in] act_info (Optional) Activation layer information in case of a fused activation.
*
*/
void configure(const CLCompileContext &compile_context,
ITensorInfo *src,
ITensorInfo *weights,
ITensorInfo *biases,
ITensorInfo *dst,
const PadStrideInfo &conv_info,
const ActivationLayerInfo &act_info = ActivationLayerInfo());
/** Static function to check if given info will lead to a valid configuration
*
* Similar to ClDirectConv2d::configure()
*
* @return a status
*/
static Status validate(const ITensorInfo *src,
const ITensorInfo *weights,
const ITensorInfo *biases,
const ITensorInfo *dst,
const PadStrideInfo &conv_info,
const ActivationLayerInfo &act_info = ActivationLayerInfo());
// Inherited method overridden
void run(ITensorPack &tensors) override;
private:
std::unique_ptr<IClKernel> _direct_conv_kernel{nullptr};
std::unique_ptr<IClKernel> _src_border_handler{nullptr};
std::unique_ptr<IClKernel> _activation_kernel{nullptr};
};
} // namespace opencl
} // namespace arm_compute
#endif /* ARM_COMPUTE_CL_DIRECT_CONV2D_H */
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