1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
|
/*
* Copyright (c) 2021-2024 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "pooling.hpp"
#include <cstdint>
#include <cstddef>
#if defined(__aarch64__)
namespace arm_conv {
namespace pooling {
void a64_u8q_nhwc_max_generic_depthfirst_impl(
const uint64_t,
const uint64_t n_valid_cells,
uint64_t n_channels,
const uint8_t *const *const inptrs,
uint8_t *outptr,
const Requantize32 &qp
)
{
__asm__ __volatile__(
"cmp %x[n_channels], #0x40\n"
"mov x9, #0x0\n"
"mov x28, #0x10\n" // cntb _, ALL, #1
"mov x27, #0x20\n" // cntb _, ALL, #2
"mov x26, #0x30\n" // cntb _, ALL, #3
"blt 7f\n"
"1:" // 4-vectors of channels
"lsr x25, %x[n_valid_cells], #0x2\n"
"movi v6.16b, #0x0\n"
"movi v9.16b, #0x0\n"
"mov x24, %x[inptrs]\n"
"movi v8.16b, #0x0\n"
"movi v7.16b, #0x0\n"
"cbz x25, 4f\n"
"ldp x23, x22, [x24, #0x0]\n"
"ldp x21, x20, [x24, #0x10]\n"
"subs x25, x25, #0x1\n"
"add x24, x24, #0x20\n"
"ldr q5, [x23, x9]\n"
"ldr q4, [x22, x9]\n"
"ldr q3, [x21, x9]\n"
"ldr q2, [x20, x9]\n"
"ldr q1, [x23, x28]\n"
"ldr q0, [x22, x28]\n"
"ldr q31, [x21, x28]\n"
"ldr q30, [x20, x28]\n"
"ldr q29, [x23, x27]\n"
"ldr q21, [x22, x27]\n"
"ldr q28, [x21, x27]\n"
"ldr q27, [x20, x27]\n"
"ldr q26, [x23, x26]\n"
"ldr q20, [x22, x26]\n"
"ldr q25, [x21, x26]\n"
"ldr q24, [x20, x26]\n"
"beq 3f\n"
"2:" // 4-vectors of channels: 4 inputs loop
"umax v23.16b, v5.16b, v4.16b\n"
"umax v19.16b, v3.16b, v2.16b\n"
"ldp x23, x22, [x24, #0x0]\n"
"ldp x21, x20, [x24, #0x10]\n"
"umax v22.16b, v1.16b, v0.16b\n"
"umax v18.16b, v31.16b, v30.16b\n"
"subs x25, x25, #0x1\n"
"add x24, x24, #0x20\n"
"umax v21.16b, v29.16b, v21.16b\n"
"umax v17.16b, v28.16b, v27.16b\n"
"ldr q5, [x23, x9]\n"
"ldr q4, [x22, x9]\n"
"ldr q3, [x21, x9]\n"
"ldr q2, [x20, x9]\n"
"umax v20.16b, v26.16b, v20.16b\n"
"umax v16.16b, v25.16b, v24.16b\n"
"ldr q1, [x23, x28]\n"
"ldr q0, [x22, x28]\n"
"umax v19.16b, v23.16b, v19.16b\n"
"umax v18.16b, v22.16b, v18.16b\n"
"ldr q31, [x21, x28]\n"
"ldr q30, [x20, x28]\n"
"umax v17.16b, v21.16b, v17.16b\n"
"ldr q29, [x23, x27]\n"
"ldr q21, [x22, x27]\n"
"umax v16.16b, v20.16b, v16.16b\n"
"ldr q28, [x21, x27]\n"
"ldr q27, [x20, x27]\n"
"umax v6.16b, v6.16b, v19.16b\n"
"umax v9.16b, v9.16b, v18.16b\n"
"ldr q26, [x23, x26]\n"
"ldr q20, [x22, x26]\n"
"umax v8.16b, v8.16b, v17.16b\n"
"ldr q25, [x21, x26]\n"
"ldr q24, [x20, x26]\n"
"umax v7.16b, v7.16b, v16.16b\n"
"bgt 2b\n"
"3:" // 4-vectors of channels: 4 inputs tail
"umax v23.16b, v5.16b, v4.16b\n"
"umax v19.16b, v3.16b, v2.16b\n"
"umax v22.16b, v1.16b, v0.16b\n"
"umax v18.16b, v31.16b, v30.16b\n"
"umax v21.16b, v29.16b, v21.16b\n"
"umax v17.16b, v28.16b, v27.16b\n"
"umax v20.16b, v26.16b, v20.16b\n"
"umax v16.16b, v25.16b, v24.16b\n"
"umax v19.16b, v23.16b, v19.16b\n"
"umax v18.16b, v22.16b, v18.16b\n"
"umax v17.16b, v21.16b, v17.16b\n"
"umax v16.16b, v20.16b, v16.16b\n"
"umax v6.16b, v6.16b, v19.16b\n"
"umax v9.16b, v9.16b, v18.16b\n"
"umax v8.16b, v8.16b, v17.16b\n"
"umax v7.16b, v7.16b, v16.16b\n"
"4:" // 4-vectors of channels: After loop
"ands x21, %x[n_valid_cells], #0x3\n"
"beq 6f\n"
"5:" // 4-vectors of channels: Single input loop
"ldr x20, [x24], #0x8\n"
"subs x21, x21, #0x1\n"
"ldr q19, [x20, x9]\n"
"ldr q18, [x20, x28]\n"
"ldr q17, [x20, x27]\n"
"ldr q16, [x20, x26]\n"
"umax v6.16b, v6.16b, v19.16b\n"
"umax v9.16b, v9.16b, v18.16b\n"
"umax v8.16b, v8.16b, v17.16b\n"
"umax v7.16b, v7.16b, v16.16b\n"
"bgt 5b\n"
"6:" // 4-vectors of channels: Single input loop: End
"add x21, %x[quant_params], %[offsetof_qp_input_offset]\n"
"uxtl v23.8h, v6.8b\n"
"uxtl2 v19.8h, v6.16b\n"
"add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n"
"ld1r { v6.4s }, [x21]\n"
"ld1r { v5.4s }, [x20]\n"
"uxtl v22.8h, v9.8b\n"
"uxtl2 v18.8h, v9.16b\n"
"uxtl v21.8h, v8.8b\n"
"uxtl2 v17.8h, v8.16b\n"
"add x21, %x[quant_params], %[offsetof_qp_per_layer_mul]\n"
"add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n"
"ld1r { v4.4s }, [x21]\n"
"ld1r { v3.4s }, [x20]\n"
"uxtl v20.8h, v7.8b\n"
"uxtl2 v16.8h, v7.16b\n"
"neg v6.4s, v6.4s\n"
"add x20, %x[quant_params], %[offsetof_qp_output_offset]\n"
"movi v2.4s, #0x0\n"
"sub %x[n_channels], %x[n_channels], #0x40\n"
"ld1r { v1.4s }, [x20]\n"
"movi v0.4s, #0xff\n"
"cmp %x[n_channels], #0x40\n"
"saddw v31.4s, v6.4s, v23.4h\n"
"saddw2 v23.4s, v6.4s, v23.8h\n"
"saddw v30.4s, v6.4s, v19.4h\n"
"saddw2 v19.4s, v6.4s, v19.8h\n"
"saddw v29.4s, v6.4s, v22.4h\n"
"saddw2 v22.4s, v6.4s, v22.8h\n"
"saddw v28.4s, v6.4s, v18.4h\n"
"saddw2 v18.4s, v6.4s, v18.8h\n"
"saddw v27.4s, v6.4s, v21.4h\n"
"saddw2 v21.4s, v6.4s, v21.8h\n"
"saddw v26.4s, v6.4s, v17.4h\n"
"saddw2 v17.4s, v6.4s, v17.8h\n"
"saddw v25.4s, v6.4s, v20.4h\n"
"saddw2 v20.4s, v6.4s, v20.8h\n"
"saddw v24.4s, v6.4s, v16.4h\n"
"saddw2 v16.4s, v6.4s, v16.8h\n"
"srshl v31.4s, v31.4s, v5.4s\n"
"srshl v23.4s, v23.4s, v5.4s\n"
"srshl v30.4s, v30.4s, v5.4s\n"
"srshl v19.4s, v19.4s, v5.4s\n"
"srshl v29.4s, v29.4s, v5.4s\n"
"srshl v22.4s, v22.4s, v5.4s\n"
"srshl v28.4s, v28.4s, v5.4s\n"
"srshl v18.4s, v18.4s, v5.4s\n"
"srshl v27.4s, v27.4s, v5.4s\n"
"srshl v21.4s, v21.4s, v5.4s\n"
"srshl v26.4s, v26.4s, v5.4s\n"
"srshl v17.4s, v17.4s, v5.4s\n"
"srshl v25.4s, v25.4s, v5.4s\n"
"srshl v20.4s, v20.4s, v5.4s\n"
"srshl v24.4s, v24.4s, v5.4s\n"
"srshl v16.4s, v16.4s, v5.4s\n"
"sqrdmulh v31.4s, v31.4s, v4.4s\n"
"sqrdmulh v23.4s, v23.4s, v4.4s\n"
"sqrdmulh v30.4s, v30.4s, v4.4s\n"
"sqrdmulh v19.4s, v19.4s, v4.4s\n"
"sqrdmulh v29.4s, v29.4s, v4.4s\n"
"sqrdmulh v22.4s, v22.4s, v4.4s\n"
"sqrdmulh v28.4s, v28.4s, v4.4s\n"
"sqrdmulh v18.4s, v18.4s, v4.4s\n"
"sqrdmulh v27.4s, v27.4s, v4.4s\n"
"sqrdmulh v21.4s, v21.4s, v4.4s\n"
"sqrdmulh v26.4s, v26.4s, v4.4s\n"
"sqrdmulh v17.4s, v17.4s, v4.4s\n"
"sqrdmulh v25.4s, v25.4s, v4.4s\n"
"sqrdmulh v20.4s, v20.4s, v4.4s\n"
"sqrdmulh v24.4s, v24.4s, v4.4s\n"
"sqrdmulh v16.4s, v16.4s, v4.4s\n"
"srshl v31.4s, v31.4s, v3.4s\n"
"srshl v23.4s, v23.4s, v3.4s\n"
"srshl v30.4s, v30.4s, v3.4s\n"
"srshl v19.4s, v19.4s, v3.4s\n"
"srshl v29.4s, v29.4s, v3.4s\n"
"srshl v22.4s, v22.4s, v3.4s\n"
"srshl v28.4s, v28.4s, v3.4s\n"
"srshl v18.4s, v18.4s, v3.4s\n"
"srshl v27.4s, v27.4s, v3.4s\n"
"srshl v21.4s, v21.4s, v3.4s\n"
"srshl v26.4s, v26.4s, v3.4s\n"
"srshl v17.4s, v17.4s, v3.4s\n"
"srshl v25.4s, v25.4s, v3.4s\n"
"srshl v20.4s, v20.4s, v3.4s\n"
"srshl v24.4s, v24.4s, v3.4s\n"
"srshl v16.4s, v16.4s, v3.4s\n"
"add v31.4s, v31.4s, v1.4s\n"
"add v23.4s, v23.4s, v1.4s\n"
"add v30.4s, v30.4s, v1.4s\n"
"add v19.4s, v19.4s, v1.4s\n"
"add v29.4s, v29.4s, v1.4s\n"
"add v22.4s, v22.4s, v1.4s\n"
"add v28.4s, v28.4s, v1.4s\n"
"add v18.4s, v18.4s, v1.4s\n"
"add v27.4s, v27.4s, v1.4s\n"
"add v21.4s, v21.4s, v1.4s\n"
"add v26.4s, v26.4s, v1.4s\n"
"add v17.4s, v17.4s, v1.4s\n"
"add v25.4s, v25.4s, v1.4s\n"
"add v20.4s, v20.4s, v1.4s\n"
"add v24.4s, v24.4s, v1.4s\n"
"add v16.4s, v16.4s, v1.4s\n"
"smax v31.4s, v31.4s, v2.4s\n"
"smax v23.4s, v23.4s, v2.4s\n"
"smax v30.4s, v30.4s, v2.4s\n"
"smax v19.4s, v19.4s, v2.4s\n"
"smax v29.4s, v29.4s, v2.4s\n"
"smax v22.4s, v22.4s, v2.4s\n"
"smax v28.4s, v28.4s, v2.4s\n"
"smax v18.4s, v18.4s, v2.4s\n"
"smax v27.4s, v27.4s, v2.4s\n"
"smax v21.4s, v21.4s, v2.4s\n"
"smax v26.4s, v26.4s, v2.4s\n"
"smax v17.4s, v17.4s, v2.4s\n"
"smax v25.4s, v25.4s, v2.4s\n"
"smax v20.4s, v20.4s, v2.4s\n"
"smax v24.4s, v24.4s, v2.4s\n"
"smax v16.4s, v16.4s, v2.4s\n"
"smin v31.4s, v31.4s, v0.4s\n"
"smin v23.4s, v23.4s, v0.4s\n"
"smin v30.4s, v30.4s, v0.4s\n"
"smin v19.4s, v19.4s, v0.4s\n"
"smin v29.4s, v29.4s, v0.4s\n"
"smin v22.4s, v22.4s, v0.4s\n"
"smin v28.4s, v28.4s, v0.4s\n"
"smin v18.4s, v18.4s, v0.4s\n"
"smin v27.4s, v27.4s, v0.4s\n"
"smin v21.4s, v21.4s, v0.4s\n"
"smin v26.4s, v26.4s, v0.4s\n"
"smin v17.4s, v17.4s, v0.4s\n"
"smin v25.4s, v25.4s, v0.4s\n"
"smin v20.4s, v20.4s, v0.4s\n"
"smin v24.4s, v24.4s, v0.4s\n"
"smin v16.4s, v16.4s, v0.4s\n"
"uzp1 v23.16b, v31.16b, v23.16b\n"
"uzp1 v19.16b, v30.16b, v19.16b\n"
"uzp1 v22.16b, v29.16b, v22.16b\n"
"uzp1 v18.16b, v28.16b, v18.16b\n"
"uzp1 v21.16b, v27.16b, v21.16b\n"
"uzp1 v17.16b, v26.16b, v17.16b\n"
"uzp1 v20.16b, v25.16b, v20.16b\n"
"uzp1 v16.16b, v24.16b, v16.16b\n"
"uzp1 v19.16b, v23.16b, v19.16b\n"
"uzp1 v18.16b, v22.16b, v18.16b\n"
"uzp1 v17.16b, v21.16b, v17.16b\n"
"uzp1 v16.16b, v20.16b, v16.16b\n"
"str q19, [%x[outptr], x9]\n"
"add x9, x9, #0x40\n"
"str q18, [%x[outptr], x28]\n"
"add x28, x28, #0x40\n"
"str q17, [%x[outptr], x27]\n"
"add x27, x27, #0x40\n"
"str q16, [%x[outptr], x26]\n"
"add x26, x26, #0x40\n"
"bge 1b\n"
"cbz %x[n_channels], 43f\n"
"7:" // Single vector of channels
"cmp %x[n_channels], #0x10\n"
"blt 14f\n"
"8:" // Single vector of channels: Loop
"lsr x25, %x[n_valid_cells], #0x2\n"
"movi v6.16b, #0x0\n"
"mov x24, %x[inptrs]\n"
"cbz x25, 11f\n"
"ldp x23, x22, [x24, #0x0]\n"
"ldp x21, x20, [x24, #0x10]\n"
"subs x25, x25, #0x1\n"
"add x24, x24, #0x20\n"
"ldr q5, [x23, x9]\n"
"ldr q4, [x22, x9]\n"
"ldr q3, [x21, x9]\n"
"ldr q2, [x20, x9]\n"
"beq 10f\n"
"9:" // Single vector of channels: Loop: 4 inputs loop
"umax v17.16b, v5.16b, v4.16b\n"
"umax v16.16b, v3.16b, v2.16b\n"
"ldp x23, x22, [x24, #0x0]\n"
"ldp x21, x20, [x24, #0x10]\n"
"subs x25, x25, #0x1\n"
"add x24, x24, #0x20\n"
"ldr q5, [x23, x9]\n"
"ldr q4, [x22, x9]\n"
"ldr q3, [x21, x9]\n"
"ldr q2, [x20, x9]\n"
"umax v16.16b, v17.16b, v16.16b\n"
"umax v6.16b, v6.16b, v16.16b\n"
"bgt 9b\n"
"10:" // Single vector of channels: Loop: 4 inputs tail
"umax v17.16b, v5.16b, v4.16b\n"
"umax v16.16b, v3.16b, v2.16b\n"
"umax v16.16b, v17.16b, v16.16b\n"
"umax v6.16b, v6.16b, v16.16b\n"
"11:" // Single vector of channels: Loop: After loop
"ands x21, %x[n_valid_cells], #0x3\n"
"beq 13f\n"
"12:" // Single vector of channels: Loop: Single input loop
"ldr x20, [x24], #0x8\n"
"subs x21, x21, #0x1\n"
"ldr q16, [x20, x9]\n"
"umax v6.16b, v6.16b, v16.16b\n"
"bgt 12b\n"
"13:" // Single vector of channels: Loop: Single input loop: End
"add x21, %x[quant_params], %[offsetof_qp_input_offset]\n"
"uxtl v17.8h, v6.8b\n"
"uxtl2 v26.8h, v6.16b\n"
"add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n"
"ld1r { v16.4s }, [x21]\n"
"ld1r { v25.4s }, [x20]\n"
"add x21, %x[quant_params], %[offsetof_qp_per_layer_mul]\n"
"add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n"
"ld1r { v24.4s }, [x21]\n"
"ld1r { v23.4s }, [x20]\n"
"add x20, %x[quant_params], %[offsetof_qp_output_offset]\n"
"movi v22.4s, #0x0\n"
"ld1r { v21.4s }, [x20]\n"
"movi v20.4s, #0xff\n"
"sub %x[n_channels], %x[n_channels], #0x10\n"
"neg v16.4s, v16.4s\n"
"cmp %x[n_channels], #0x10\n"
"saddw v19.4s, v16.4s, v17.4h\n"
"saddw2 v17.4s, v16.4s, v17.8h\n"
"saddw v18.4s, v16.4s, v26.4h\n"
"saddw2 v16.4s, v16.4s, v26.8h\n"
"srshl v19.4s, v19.4s, v25.4s\n"
"srshl v17.4s, v17.4s, v25.4s\n"
"srshl v18.4s, v18.4s, v25.4s\n"
"srshl v16.4s, v16.4s, v25.4s\n"
"sqrdmulh v19.4s, v19.4s, v24.4s\n"
"sqrdmulh v17.4s, v17.4s, v24.4s\n"
"sqrdmulh v18.4s, v18.4s, v24.4s\n"
"sqrdmulh v16.4s, v16.4s, v24.4s\n"
"srshl v19.4s, v19.4s, v23.4s\n"
"srshl v17.4s, v17.4s, v23.4s\n"
"srshl v18.4s, v18.4s, v23.4s\n"
"srshl v16.4s, v16.4s, v23.4s\n"
"add v19.4s, v19.4s, v21.4s\n"
"add v17.4s, v17.4s, v21.4s\n"
"add v18.4s, v18.4s, v21.4s\n"
"add v16.4s, v16.4s, v21.4s\n"
"smax v19.4s, v19.4s, v22.4s\n"
"smax v17.4s, v17.4s, v22.4s\n"
"smax v18.4s, v18.4s, v22.4s\n"
"smax v16.4s, v16.4s, v22.4s\n"
"smin v19.4s, v19.4s, v20.4s\n"
"smin v17.4s, v17.4s, v20.4s\n"
"smin v18.4s, v18.4s, v20.4s\n"
"smin v16.4s, v16.4s, v20.4s\n"
"uzp1 v17.16b, v19.16b, v17.16b\n"
"uzp1 v16.16b, v18.16b, v16.16b\n"
"uzp1 v16.16b, v17.16b, v16.16b\n"
"str q16, [%x[outptr], x9]\n"
"add x9, x9, #0x10\n"
"bge 8b\n"
"cbz %x[n_channels], 43f\n"
"14:" // Oddments
"lsr x25, %x[n_valid_cells], #0x2\n"
"add %x[outptr], %x[outptr], x9\n"
"movi v6.16b, #0x0\n"
"mov x24, %x[inptrs]\n"
"cbz x25, 24f\n"
"15:" // Oddments: 4 inputs loop
"ldp x23, x22, [x24, #0x0]\n"
"ldp x21, x20, [x24, #0x10]\n"
"add x24, x24, #0x20\n"
"movi v5.16b, #0x0\n"
"movi v4.16b, #0x0\n"
"movi v3.16b, #0x0\n"
"movi v2.16b, #0x0\n"
"add x23, x23, x9\n"
"add x22, x22, x9\n"
"add x21, x21, x9\n"
"add x20, x20, x9\n"
"tbz %x[n_channels], #3, 19f\n"
"ldr d5, [x23], #0x8\n"
"ldr d4, [x22], #0x8\n"
"ldr d3, [x21], #0x8\n"
"ldr d2, [x20], #0x8\n"
"tbz %x[n_channels], #2, 17f\n"
"ld1 { v5.s }[2], [x23], #0x4\n"
"ld1 { v4.s }[2], [x22], #0x4\n"
"ld1 { v3.s }[2], [x21], #0x4\n"
"ld1 { v2.s }[2], [x20], #0x4\n"
"tbz %x[n_channels], #1, 16f\n"
"ld1 { v5.h }[6], [x23], #0x2\n"
"ld1 { v4.h }[6], [x22], #0x2\n"
"ld1 { v3.h }[6], [x21], #0x2\n"
"ld1 { v2.h }[6], [x20], #0x2\n"
"tbz %x[n_channels], #0, 23f\n"
"ld1 { v5.b }[14], [x23], #0x1\n"
"ld1 { v4.b }[14], [x22], #0x1\n"
"ld1 { v3.b }[14], [x21], #0x1\n"
"ld1 { v2.b }[14], [x20], #0x1\n"
"b 23f\n"
"16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset
"tbz %x[n_channels], #0, 23f\n"
"ld1 { v5.b }[12], [x23], #0x1\n"
"ld1 { v4.b }[12], [x22], #0x1\n"
"ld1 { v3.b }[12], [x21], #0x1\n"
"ld1 { v2.b }[12], [x20], #0x1\n"
"b 23f\n"
"17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset
"tbz %x[n_channels], #1, 18f\n"
"ld1 { v5.h }[4], [x23], #0x2\n"
"ld1 { v4.h }[4], [x22], #0x2\n"
"ld1 { v3.h }[4], [x21], #0x2\n"
"ld1 { v2.h }[4], [x20], #0x2\n"
"tbz %x[n_channels], #0, 23f\n"
"ld1 { v5.b }[10], [x23], #0x1\n"
"ld1 { v4.b }[10], [x22], #0x1\n"
"ld1 { v3.b }[10], [x21], #0x1\n"
"ld1 { v2.b }[10], [x20], #0x1\n"
"b 23f\n"
"18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset
"tbz %x[n_channels], #0, 23f\n"
"ld1 { v5.b }[8], [x23], #0x1\n"
"ld1 { v4.b }[8], [x22], #0x1\n"
"ld1 { v3.b }[8], [x21], #0x1\n"
"ld1 { v2.b }[8], [x20], #0x1\n"
"b 23f\n"
"19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset
"tbz %x[n_channels], #2, 21f\n"
"ldr s5, [x23], #0x4\n"
"ldr s4, [x22], #0x4\n"
"ldr s3, [x21], #0x4\n"
"ldr s2, [x20], #0x4\n"
"tbz %x[n_channels], #1, 20f\n"
"ld1 { v5.h }[2], [x23], #0x2\n"
"ld1 { v4.h }[2], [x22], #0x2\n"
"ld1 { v3.h }[2], [x21], #0x2\n"
"ld1 { v2.h }[2], [x20], #0x2\n"
"tbz %x[n_channels], #0, 23f\n"
"ld1 { v5.b }[6], [x23], #0x1\n"
"ld1 { v4.b }[6], [x22], #0x1\n"
"ld1 { v3.b }[6], [x21], #0x1\n"
"ld1 { v2.b }[6], [x20], #0x1\n"
"b 23f\n"
"20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset
"tbz %x[n_channels], #0, 23f\n"
"ld1 { v5.b }[4], [x23], #0x1\n"
"ld1 { v4.b }[4], [x22], #0x1\n"
"ld1 { v3.b }[4], [x21], #0x1\n"
"ld1 { v2.b }[4], [x20], #0x1\n"
"b 23f\n"
"21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset
"tbz %x[n_channels], #1, 22f\n"
"ldr h5, [x23], #0x2\n"
"ldr h4, [x22], #0x2\n"
"ldr h3, [x21], #0x2\n"
"ldr h2, [x20], #0x2\n"
"tbz %x[n_channels], #0, 23f\n"
"ld1 { v5.b }[2], [x23], #0x1\n"
"ld1 { v4.b }[2], [x22], #0x1\n"
"ld1 { v3.b }[2], [x21], #0x1\n"
"ld1 { v2.b }[2], [x20], #0x1\n"
"b 23f\n"
"22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
"tbz %x[n_channels], #0, 23f\n"
"ldr b5, [x23], #0x1\n"
"ldr b4, [x22], #0x1\n"
"ldr b3, [x21], #0x1\n"
"ldr b2, [x20], #0x1\n"
"23:" // Oddments: 4 inputs loop: Load: Bit 3: End
"umax v17.16b, v5.16b, v4.16b\n"
"umax v16.16b, v3.16b, v2.16b\n"
"subs x25, x25, #0x1\n"
"umax v16.16b, v17.16b, v16.16b\n"
"umax v6.16b, v6.16b, v16.16b\n"
"bgt 15b\n"
"24:" // Oddments: After loop
"ands x21, %x[n_valid_cells], #0x3\n"
"beq 34f\n"
"25:" // Oddments: Single input loop
"ldr x23, [x24], #0x8\n"
"movi v5.16b, #0x0\n"
"add x23, x23, x9\n"
"tbz %x[n_channels], #3, 29f\n"
"ldr d5, [x23], #0x8\n"
"tbz %x[n_channels], #2, 27f\n"
"ld1 { v5.s }[2], [x23], #0x4\n"
"tbz %x[n_channels], #1, 26f\n"
"ld1 { v5.h }[6], [x23], #0x2\n"
"tbz %x[n_channels], #0, 33f\n"
"ld1 { v5.b }[14], [x23], #0x1\n"
"b 33f\n"
"26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset
"tbz %x[n_channels], #0, 33f\n"
"ld1 { v5.b }[12], [x23], #0x1\n"
"b 33f\n"
"27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset
"tbz %x[n_channels], #1, 28f\n"
"ld1 { v5.h }[4], [x23], #0x2\n"
"tbz %x[n_channels], #0, 33f\n"
"ld1 { v5.b }[10], [x23], #0x1\n"
"b 33f\n"
"28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset
"tbz %x[n_channels], #0, 33f\n"
"ld1 { v5.b }[8], [x23], #0x1\n"
"b 33f\n"
"29:" // Oddments: Single input loop: Load: Bit 3: Unset
"tbz %x[n_channels], #2, 31f\n"
"ldr s5, [x23], #0x4\n"
"tbz %x[n_channels], #1, 30f\n"
"ld1 { v5.h }[2], [x23], #0x2\n"
"tbz %x[n_channels], #0, 33f\n"
"ld1 { v5.b }[6], [x23], #0x1\n"
"b 33f\n"
"30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset
"tbz %x[n_channels], #0, 33f\n"
"ld1 { v5.b }[4], [x23], #0x1\n"
"b 33f\n"
"31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset
"tbz %x[n_channels], #1, 32f\n"
"ldr h5, [x23], #0x2\n"
"tbz %x[n_channels], #0, 33f\n"
"ld1 { v5.b }[2], [x23], #0x1\n"
"b 33f\n"
"32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
"tbz %x[n_channels], #0, 33f\n"
"ldr b5, [x23], #0x1\n"
"33:" // Oddments: Single input loop: Load: Bit 3: End
"subs x21, x21, #0x1\n"
"umax v6.16b, v6.16b, v5.16b\n"
"bgt 25b\n"
"34:" // Oddments: Single input loop: End
"add x21, %x[quant_params], %[offsetof_qp_input_offset]\n"
"uxtl v17.8h, v6.8b\n"
"uxtl2 v26.8h, v6.16b\n"
"add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n"
"ld1r { v16.4s }, [x21]\n"
"ld1r { v25.4s }, [x20]\n"
"add x21, %x[quant_params], %[offsetof_qp_per_layer_mul]\n"
"add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n"
"ld1r { v24.4s }, [x21]\n"
"ld1r { v23.4s }, [x20]\n"
"add x20, %x[quant_params], %[offsetof_qp_output_offset]\n"
"movi v22.4s, #0x0\n"
"ld1r { v21.4s }, [x20]\n"
"movi v20.4s, #0xff\n"
"neg v16.4s, v16.4s\n"
"saddw v19.4s, v16.4s, v17.4h\n"
"saddw2 v17.4s, v16.4s, v17.8h\n"
"saddw v18.4s, v16.4s, v26.4h\n"
"saddw2 v16.4s, v16.4s, v26.8h\n"
"srshl v19.4s, v19.4s, v25.4s\n"
"srshl v17.4s, v17.4s, v25.4s\n"
"srshl v18.4s, v18.4s, v25.4s\n"
"srshl v16.4s, v16.4s, v25.4s\n"
"sqrdmulh v19.4s, v19.4s, v24.4s\n"
"sqrdmulh v17.4s, v17.4s, v24.4s\n"
"sqrdmulh v18.4s, v18.4s, v24.4s\n"
"sqrdmulh v16.4s, v16.4s, v24.4s\n"
"srshl v19.4s, v19.4s, v23.4s\n"
"srshl v17.4s, v17.4s, v23.4s\n"
"srshl v18.4s, v18.4s, v23.4s\n"
"srshl v16.4s, v16.4s, v23.4s\n"
"add v19.4s, v19.4s, v21.4s\n"
"add v17.4s, v17.4s, v21.4s\n"
"add v18.4s, v18.4s, v21.4s\n"
"add v16.4s, v16.4s, v21.4s\n"
"smax v19.4s, v19.4s, v22.4s\n"
"smax v17.4s, v17.4s, v22.4s\n"
"smax v18.4s, v18.4s, v22.4s\n"
"smax v16.4s, v16.4s, v22.4s\n"
"smin v19.4s, v19.4s, v20.4s\n"
"smin v17.4s, v17.4s, v20.4s\n"
"smin v18.4s, v18.4s, v20.4s\n"
"smin v16.4s, v16.4s, v20.4s\n"
"uzp1 v17.16b, v19.16b, v17.16b\n"
"uzp1 v16.16b, v18.16b, v16.16b\n"
"uzp1 v16.16b, v17.16b, v16.16b\n"
"tbz %x[n_channels], #3, 38f\n"
"st1 { v16.d }[0], [%x[outptr]], #0x8\n"
"tbz %x[n_channels], #2, 36f\n"
"st1 { v16.s }[2], [%x[outptr]], #0x4\n"
"tbz %x[n_channels], #1, 35f\n"
"st1 { v16.h }[6], [%x[outptr]], #0x2\n"
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[14], [%x[outptr]], #0x1\n"
"b 42f\n"
"35:" // Oddments: Store: Bit 3: Bit 2: Bit 1: Unset
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[12], [%x[outptr]], #0x1\n"
"b 42f\n"
"36:" // Oddments: Store: Bit 3: Bit 2: Unset
"tbz %x[n_channels], #1, 37f\n"
"st1 { v16.h }[4], [%x[outptr]], #0x2\n"
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[10], [%x[outptr]], #0x1\n"
"b 42f\n"
"37:" // Oddments: Store: Bit 3: Bit 2: Unset: Bit 1: Unset
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[8], [%x[outptr]], #0x1\n"
"b 42f\n"
"38:" // Oddments: Store: Bit 3: Unset
"tbz %x[n_channels], #2, 40f\n"
"st1 { v16.s }[0], [%x[outptr]], #0x4\n"
"tbz %x[n_channels], #1, 39f\n"
"st1 { v16.h }[2], [%x[outptr]], #0x2\n"
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[6], [%x[outptr]], #0x1\n"
"b 42f\n"
"39:" // Oddments: Store: Bit 3: Unset: Bit 2: Bit 1: Unset
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[4], [%x[outptr]], #0x1\n"
"b 42f\n"
"40:" // Oddments: Store: Bit 3: Unset: Bit 2: Unset
"tbz %x[n_channels], #1, 41f\n"
"st1 { v16.h }[0], [%x[outptr]], #0x2\n"
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[2], [%x[outptr]], #0x1\n"
"b 42f\n"
"41:" // Oddments: Store: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
"tbz %x[n_channels], #0, 42f\n"
"st1 { v16.b }[0], [%x[outptr]], #0x1\n"
"42:" // Oddments: Store: Bit 3: End
"43:" // End
: [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr)
: [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_input_offset] "I" (offsetof(Requantize32, input_offset)), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [quant_params] "r" (&qp)
: "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}
} // namespace pooling
} // namespace arm_conv
#endif // defined(__aarch64__)
|