From 631c41a4e3645a948b0f597caa77e8fa91ca0efc Mon Sep 17 00:00:00 2001 From: Georgios Pinitas Date: Wed, 6 Dec 2017 11:53:03 +0000 Subject: COMPMID-556: Rename Error to Status and inverse logic Change-Id: Ib57d4f7177cc6179302bda7ad870acb8bd3825f5 Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/112115 Tested-by: BSG Visual Compute Jenkins server to access repositories on http://mpd-gerrit.cambridge.arm.com Reviewed-by: Anthony Barbier --- tests/validation/CL/ArithmeticAddition.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/validation/CL/ArithmeticAddition.cpp') diff --git a/tests/validation/CL/ArithmeticAddition.cpp b/tests/validation/CL/ArithmeticAddition.cpp index 61b3b06d74..787b1b986f 100644 --- a/tests/validation/CL/ArithmeticAddition.cpp +++ b/tests/validation/CL/ArithmeticAddition.cpp @@ -88,7 +88,7 @@ DATA_TEST_CASE(Validate, framework::DatasetMode::ALL, zip(zip(zip( TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::QS8, 3), TensorInfo(TensorShape(32U, 13U, 2U), 1, DataType::QS8, 2), })), - framework::dataset::make("Expected", { false, false, true, true, true, true, false })), + framework::dataset::make("Expected", { true, true, false, false, false, false, true })), input1_info, input2_info, output_info, expected) { ARM_COMPUTE_EXPECT(bool(CLArithmeticAddition::validate(&input1_info.clone()->set_is_resizable(false), &input2_info.clone()->set_is_resizable(false), &output_info.clone()->set_is_resizable(false), ConvertPolicy::WRAP)) == expected, framework::LogLevel::ERRORS); -- cgit v1.2.1