From a35980546c00ae1647ce033b061530607a5ad1e4 Mon Sep 17 00:00:00 2001 From: morgolock Date: Tue, 31 Dec 2019 12:20:47 +0000 Subject: COMPMID-2994: Add support QASYMM8_SIGNED in NEElementwiseMax Change-Id: I8261558384ae028f7f016dfd6715de140f0b6445 Signed-off-by: morgolock Reviewed-on: https://review.mlplatform.org/c/2528 Comments-Addressed: Arm Jenkins Tested-by: Arm Jenkins Reviewed-by: Michele Di Giorgio --- src/core/NEON/kernels/NEElementwiseOperationKernel.cpp | 6 ++---- src/runtime/NEON/functions/NEElementwiseOperators.cpp | 6 ++++++ 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/core/NEON/kernels/NEElementwiseOperationKernel.cpp b/src/core/NEON/kernels/NEElementwiseOperationKernel.cpp index 4928ae9bdd..b8e6f0cc69 100644 --- a/src/core/NEON/kernels/NEElementwiseOperationKernel.cpp +++ b/src/core/NEON/kernels/NEElementwiseOperationKernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019 ARM Limited. + * Copyright (c) 2018-2020 ARM Limited. * * SPDX-License-Identifier: MIT * @@ -795,8 +795,7 @@ void elementwise_op_quantized_signed(const ITensor *in1, const ITensor *in2, ITe const UniformQuantizationInfo output_qinfo = out->info()->quantization_info().uniform(); - // Output quantization info (add 0.5 to round toward the nearest integer - 0.5 rounds away from zero) - const float32x4_t voffseto = vdupq_n_f32(output_qinfo.offset + 0.5f); + const float32x4_t voffseto = vdupq_n_f32(output_qinfo.offset); const float32x4_t invvscaleo = vdupq_n_f32(1.f / output_qinfo.scale); if(is_broadcast_across_x) @@ -1000,7 +999,6 @@ NEElementwiseOperationKernel::NEElementwiseOperationKernel() Status NEElementwiseOperationKernel::validate_arguments_common(const ITensorInfo &input1, const ITensorInfo &input2, const ITensorInfo &output) { ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(&input1, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::S16, DataType::F16, DataType::S32, DataType::F32); - ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(&input2, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::S16, DataType::F16, DataType::S32, DataType::F32); ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(&input1); ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(&input1, &input2); diff --git a/src/runtime/NEON/functions/NEElementwiseOperators.cpp b/src/runtime/NEON/functions/NEElementwiseOperators.cpp index 699363111d..ede8c20428 100644 --- a/src/runtime/NEON/functions/NEElementwiseOperators.cpp +++ b/src/runtime/NEON/functions/NEElementwiseOperators.cpp @@ -23,6 +23,7 @@ */ #include "arm_compute/runtime/NEON/functions/NEElementwiseOperations.h" #include +#include "arm_compute/core/Validate.h" #include "arm_compute/core/ITensor.h" #include "support/ToolchainSupport.h" @@ -40,6 +41,11 @@ void NEElementwiseMax::configure(ITensor *input1, ITensor *input2, ITensor *outp Status NEElementwiseMax::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output) { + if( input1->data_type() == DataType::QASYMM8_SIGNED) + { + ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input1, output); + ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_QUANTIZATION_INFO(input1, input2, output); + } return NEArithmeticOperationKernel::validate(ArithmeticOperation::MAX, input1, input2, output); } -- cgit v1.2.1