From 4d55e0a3e848db25496b31529f4405bee7115cf8 Mon Sep 17 00:00:00 2001 From: Pablo Tello Date: Fri, 10 Nov 2017 15:57:14 +0000 Subject: COMPMID-677: Integrate HGEMM assembly kernel (generic CPUs) Change-Id: I39abf367fe7ea1a54475e2ac0ecec12e90806899 Reviewed-on: http://mpd-gerrit.cambridge.arm.com/95378 Tested-by: Kaizen Reviewed-by: Anthony Barbier --- .../kernels/arm64/NEHGEMMAArch64FP16Kernel.cpp | 133 +++++++++++++++++++++ src/runtime/NEON/functions/NEGEMM.cpp | 31 ++++- 2 files changed, 160 insertions(+), 4 deletions(-) create mode 100644 src/core/NEON/kernels/arm64/NEHGEMMAArch64FP16Kernel.cpp (limited to 'src') diff --git a/src/core/NEON/kernels/arm64/NEHGEMMAArch64FP16Kernel.cpp b/src/core/NEON/kernels/arm64/NEHGEMMAArch64FP16Kernel.cpp new file mode 100644 index 0000000000..225630434b --- /dev/null +++ b/src/core/NEON/kernels/arm64/NEHGEMMAArch64FP16Kernel.cpp @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/core/NEON/kernels/arm64/NEHGEMMAArch64FP16Kernel.h" + +#include "arm_compute/core/AccessWindowStatic.h" +#include "arm_compute/core/AccessWindowTranspose.h" +#include "arm_compute/core/Error.h" +#include "arm_compute/core/Helpers.h" +#include "arm_compute/core/IAccessWindow.h" +#include "arm_compute/core/ITensor.h" +#include "arm_compute/core/NEON/NEFixedPoint.h" +#include "arm_compute/core/TensorInfo.h" +#include "arm_compute/core/Types.h" +#include "arm_compute/core/Utils.h" +#include "arm_compute/core/Validate.h" +#include "arm_compute/core/Window.h" +#include "support/ToolchainSupport.h" + +namespace arm_compute +{ +#include "arm_compute/core/NEON/kernels/assembly/gemm_interleaved.hpp" +#include "arm_compute/core/NEON/kernels/assembly/kernels/a64_hgemm_24x8.hpp" +} // namespace arm_compute + +#include +#include +#include +#include + +namespace arm_compute +{ +void NEHGEMMAArch64FP16Kernel::internal_configure(const ITensor *input0, const ITensor *input1, ITensor *output, ITensor *workspace, float alpha, float beta, bool transform_0, bool transform_1) +{ + ARM_COMPUTE_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input0, 1, DataType::F16); + ARM_COMPUTE_ERROR_ON_MISMATCHING_DATA_TYPES(input0, input1, output); + ARM_COMPUTE_ERROR_ON_MISMATCHING_FIXED_POINT(input0, input1, output); + + _input0 = input0; + _input1 = input1; + _output = output; + _workspace = workspace; + _alpha = alpha; + _beta = beta; + _transform_0 = transform_0; + _transform_1 = transform_1; + + // Configure kernel window + Window win = calculate_max_window(*output->info()); + + AccessWindowRectangle output_access(output->info(), 0, 0, 24, 8); + + const int input0_access_end = ceil_to_multiple(input0->info()->tensor_shape().x(), 8); + const int input1_access_end = ceil_to_multiple(input1->info()->tensor_shape().x(), 24); + + update_window_and_padding(win, + AccessWindowStatic(input0->info(), 0, 0, input0_access_end, input0->info()->tensor_shape().y()), + AccessWindowStatic(input1->info(), 0, 0, input1_access_end, input1->info()->tensor_shape().y()), + output_access); + + INEKernel::configure(win); +} + +void NEHGEMMAArch64FP16Kernel::run(const Window &window, const ThreadInfo &info) +{ +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this); + ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(INEKernel::window(), window); + + const int lda = _input0->info()->strides_in_bytes().y() / sizeof(hgemm_24x8::operand_type); + const int ldb = _input1->info()->strides_in_bytes().y() / sizeof(hgemm_24x8::operand_type); + const int ldc = _output->info()->strides_in_bytes().y() / sizeof(hgemm_24x8::result_type); + + const auto in1_ptr = reinterpret_cast(_input1->buffer()); + + const int M = std::min(_output->info()->tensor_shape().y(), static_cast(window.y().end())) - window.y().start(); + const int N = _output->info()->tensor_shape().x(); + const int K = _input0->info()->tensor_shape().x(); + + // Only iterate over batches + Window win(window); + win.set(0, Window::Dimension(0, 1, 1)); + win.set(1, Window::Dimension(0, 1, 1)); + + Iterator in0(_input0, window); + Iterator out(_output, window); + + GemmInterleaved gemm(&info.cpu_info, M, N, K, !_transform_0, !_transform_1); + constexpr size_t alignment = 4096; + const size_t offset = (gemm.get_working_size() + alignment - 1) * info.thread_id; + void *workspace = _workspace->buffer() + offset; + size_t workspace_size = _workspace->info()->total_size(); + + if(support::cpp11::align(alignment, gemm.get_working_size(), workspace, workspace_size) == nullptr) + { + ARM_COMPUTE_ERROR("Not enough space to align buffer!"); + } + + execute_window_loop(win, [&](const Coordinates & id) + { + gemm.execute(reinterpret_cast(in0.ptr()), lda, + reinterpret_cast(in1_ptr), ldb, + reinterpret_cast(out.ptr()), ldc, + _alpha, 1.f, workspace); + }, + in0, out); +#else /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + ARM_COMPUTE_UNUSED(window); + ARM_COMPUTE_UNUSED(info); + ARM_COMPUTE_ERROR("Recompile the library with arch=arm64-v8.2-a to enable support for FP16."); +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ +} +} // namespace arm_compute diff --git a/src/runtime/NEON/functions/NEGEMM.cpp b/src/runtime/NEON/functions/NEGEMM.cpp index 2dea9317a5..950f4c9899 100644 --- a/src/runtime/NEON/functions/NEGEMM.cpp +++ b/src/runtime/NEON/functions/NEGEMM.cpp @@ -28,6 +28,7 @@ #include "arm_compute/core/ITensor.h" #include "arm_compute/core/NEON/kernels/arm32/NEGEMMAArch32Kernel.h" #include "arm_compute/core/NEON/kernels/arm64/NEGEMMAArch64Kernel.h" +#include "arm_compute/core/NEON/kernels/arm64/NEHGEMMAArch64FP16Kernel.h" #include "arm_compute/core/TensorInfo.h" #include "arm_compute/core/Types.h" #include "arm_compute/core/Validate.h" @@ -39,6 +40,7 @@ namespace arm_compute { #include "arm_compute/core/NEON/kernels/assembly/gemm_interleaved.hpp" #include "arm_compute/core/NEON/kernels/assembly/kernels/a32_sgemm_8x6.hpp" +#include "arm_compute/core/NEON/kernels/assembly/kernels/a64_hgemm_24x8.hpp" #include "arm_compute/core/NEON/kernels/assembly/kernels/a64_sgemm_12x8.hpp" } // namespace arm_compute @@ -96,6 +98,14 @@ void NEGEMM::configure(const ITensor *a, const ITensor *b, const ITensor *c, ITe { _mm_optimised_kernel = support::cpp14::make_unique(); } + else if(a->info()->data_type() == DataType::F16 && (c == nullptr || beta == 0.f)) + { +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + _mm_optimised_kernel = support::cpp14::make_unique(); +#else /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + ARM_COMPUTE_ERROR("Recompile the library with arch=arm64-v8.2-a to enable support for FP16."); +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + } #endif /* defined(__arm__) || defined(__aarch64__) */ #if defined(__arm__) || defined(__aarch64__) @@ -107,19 +117,32 @@ void NEGEMM::configure(const ITensor *a, const ITensor *b, const ITensor *c, ITe const int N = d->info()->tensor_shape().x(); const int K = a->info()->tensor_shape().x(); + size_t workbench_size = 0; + #if defined(__arm__) - GemmInterleaved gemm(&ci, M, N, K, false, false); + workbench_size = GemmInterleaved(&ci, M, N, K, false, false).get_working_size(); #elif defined(__aarch64__) - GemmInterleaved gemm(&ci, M, N, K, false, false); + if(a->info()->data_type() == DataType::F32) + { + workbench_size = GemmInterleaved(&ci, M, N, K, false, false).get_working_size(); + } + else if(a->info()->data_type() == DataType::F16) + { +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + workbench_size = GemmInterleaved(&ci, M, N, K, false, false).get_working_size(); +#else /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + ARM_COMPUTE_ERROR("Recompile the library with arch=arm64-v8.2-a to enable support for FP16."); +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + } #endif /* defined(__arm__) || defined(__aarch64__) */ constexpr size_t alignment = 4096; - _workspace.allocator()->init(TensorInfo(TensorShape{ (gemm.get_working_size() + alignment - 1) * NEScheduler::get().num_threads() }, 1, DataType::S8)); + ARM_COMPUTE_ERROR_ON_MSG(workbench_size == 0, "size cannot be 0"); + _workspace.allocator()->init(TensorInfo(TensorShape{ (workbench_size + alignment - 1) * NEScheduler::get().num_threads() }, 1, DataType::S8)); _memory_group.manage(&_workspace); // Configure matrix multiplication kernel _mm_optimised_kernel->configure(a, b, d, &_workspace, alpha, 0.f); - _workspace.allocator()->allocate(); } else -- cgit v1.2.1