From 75eea338eb232ebdafa2fb84d22e711b5f964785 Mon Sep 17 00:00:00 2001 From: Sang-Hoon Park Date: Fri, 13 Nov 2020 13:44:13 +0000 Subject: COMPMID-3961: Add Logical OR/AND/NOT operator on CL Change-Id: I612aeed6affa17624fb9044964dd59c41a5c9888 Signed-off-by: Sang-Hoon Park Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4448 Reviewed-by: Pablo Marquez Tello Tested-by: Arm Jenkins Comments-Addressed: Arm Jenkins --- src/runtime/CL/functions/CLLogicalAnd.cpp | 97 +++++++++++++++++++++++++++++++ src/runtime/CL/functions/CLLogicalNot.cpp | 95 ++++++++++++++++++++++++++++++ src/runtime/CL/functions/CLLogicalOr.cpp | 97 +++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 src/runtime/CL/functions/CLLogicalAnd.cpp create mode 100644 src/runtime/CL/functions/CLLogicalNot.cpp create mode 100644 src/runtime/CL/functions/CLLogicalOr.cpp (limited to 'src/runtime') diff --git a/src/runtime/CL/functions/CLLogicalAnd.cpp b/src/runtime/CL/functions/CLLogicalAnd.cpp new file mode 100644 index 0000000000..55d3dc523b --- /dev/null +++ b/src/runtime/CL/functions/CLLogicalAnd.cpp @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/runtime/CL/functions/CLLogicalAnd.h" +#include "arm_compute/core/CL/ICLTensor.h" +#include "src/core/CL/kernels/CLElementwiseOperationKernel.h" +#include "support/MemorySupport.h" + +#include + +namespace arm_compute +{ +namespace experimental +{ +void CLLogicalAnd::configure(const CLCompileContext &compile_context, ITensorInfo *input1, ITensorInfo *input2, ITensorInfo *output) +{ + auto k = arm_compute::support::cpp14::make_unique(); + k->configure(compile_context, kernels::LogicalOperation::And, input1, input2, output); + _kernel = std::move(k); +} + +Status CLLogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output) +{ + return CLLogicalBinaryKernel::validate(kernels::LogicalOperation::And, input1, input2, output); +} + +void CLLogicalAnd::run(ITensorPack &tensors) +{ + ICLOperator::run(tensors); +} +} // namespace experimental + +struct CLLogicalAnd::Impl +{ + const ICLTensor *src0{ nullptr }; + const ICLTensor *src1{ nullptr }; + ICLTensor *dst{ nullptr }; + std::unique_ptr op{ nullptr }; +}; + +CLLogicalAnd::CLLogicalAnd() + : _impl(support::cpp14::make_unique()) +{ +} +CLLogicalAnd::CLLogicalAnd(CLLogicalAnd &&) = default; +CLLogicalAnd &CLLogicalAnd::operator=(CLLogicalAnd &&) = default; +CLLogicalAnd::~CLLogicalAnd() = default; + +void CLLogicalAnd::configure(ICLTensor *input1, ICLTensor *input2, ICLTensor *output) +{ + configure(CLKernelLibrary::get().get_compile_context(), input1, input2, output); +} + +void CLLogicalAnd::configure(const CLCompileContext &compile_context, ICLTensor *input1, ICLTensor *input2, ICLTensor *output) +{ + _impl->src0 = input1; + _impl->src1 = input2; + _impl->dst = output; + _impl->op = arm_compute::support::cpp14::make_unique(); + _impl->op->configure(compile_context, input1->info(), input2->info(), output->info()); +} + +Status CLLogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output) +{ + return experimental::CLLogicalAnd::validate(input1, input2, output); +} + +void CLLogicalAnd::run() +{ + ITensorPack pack; + pack.add_tensor(TensorType::ACL_SRC_0, _impl->src0); + pack.add_tensor(TensorType::ACL_SRC_1, _impl->src1); + pack.add_tensor(TensorType::ACL_DST, _impl->dst); + + _impl->op->run(pack); +} +} // namespace arm_compute diff --git a/src/runtime/CL/functions/CLLogicalNot.cpp b/src/runtime/CL/functions/CLLogicalNot.cpp new file mode 100644 index 0000000000..67aa3192f8 --- /dev/null +++ b/src/runtime/CL/functions/CLLogicalNot.cpp @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/runtime/CL/functions/CLLogicalNot.h" +#include "arm_compute/core/CL/ICLTensor.h" +#include "src/core/CL/kernels/CLElementWiseUnaryLayerKernel.h" +#include "support/MemorySupport.h" + +#include + +namespace arm_compute +{ +namespace experimental +{ +void CLLogicalNot::configure(const CLCompileContext &compile_context, const ITensorInfo *input, ITensorInfo *output) +{ + auto k = arm_compute::support::cpp14::make_unique(); + k->configure(compile_context, input, output, ElementWiseUnary::LOGICAL_NOT); + _kernel = std::move(k); +} + +Status CLLogicalNot::validate(const ITensorInfo *input, const ITensorInfo *output) +{ + return CLElementWiseUnaryLayerKernel::validate(input, output, ElementWiseUnary::LOGICAL_NOT); +} + +void CLLogicalNot::run(ITensorPack &tensors) +{ + ICLOperator::run(tensors); +} +} // namespace experimental + +struct CLLogicalNot::Impl +{ + const ICLTensor *src{ nullptr }; + ICLTensor *dst{ nullptr }; + std::unique_ptr op{ nullptr }; +}; + +CLLogicalNot::CLLogicalNot() + : _impl(support::cpp14::make_unique()) +{ +} +CLLogicalNot::CLLogicalNot(CLLogicalNot &&) = default; +CLLogicalNot &CLLogicalNot::operator=(CLLogicalNot &&) = default; +CLLogicalNot::~CLLogicalNot() = default; + +void CLLogicalNot::configure(const ICLTensor *input, ICLTensor *output) +{ + configure(CLKernelLibrary::get().get_compile_context(), input, output); +} + +void CLLogicalNot::configure(const CLCompileContext &compile_context, const ICLTensor *input, ICLTensor *output) +{ + _impl->src = input; + _impl->dst = output; + _impl->op = arm_compute::support::cpp14::make_unique(); + _impl->op->configure(compile_context, input->info(), output->info()); +} + +Status CLLogicalNot::validate(const ITensorInfo *input, const ITensorInfo *output) +{ + return experimental::CLLogicalNot::validate(input, output); +} + +void CLLogicalNot::run() +{ + ITensorPack pack; + pack.add_tensor(TensorType::ACL_SRC, _impl->src); + pack.add_tensor(TensorType::ACL_DST, _impl->dst); + + _impl->op->run(pack); +} + +} // namespace arm_compute \ No newline at end of file diff --git a/src/runtime/CL/functions/CLLogicalOr.cpp b/src/runtime/CL/functions/CLLogicalOr.cpp new file mode 100644 index 0000000000..4681083fd5 --- /dev/null +++ b/src/runtime/CL/functions/CLLogicalOr.cpp @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/runtime/CL/functions/CLLogicalOr.h" +#include "arm_compute/core/CL/ICLTensor.h" +#include "src/core/CL/kernels/CLElementwiseOperationKernel.h" +#include "support/MemorySupport.h" + +#include + +namespace arm_compute +{ +namespace experimental +{ +void CLLogicalOr::configure(const CLCompileContext &compile_context, ITensorInfo *input1, ITensorInfo *input2, ITensorInfo *output) +{ + auto k = arm_compute::support::cpp14::make_unique(); + k->configure(compile_context, kernels::LogicalOperation::Or, input1, input2, output); + _kernel = std::move(k); +} + +Status CLLogicalOr::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output) +{ + return CLLogicalBinaryKernel::validate(kernels::LogicalOperation::Or, input1, input2, output); +} + +void CLLogicalOr::run(ITensorPack &tensors) +{ + ICLOperator::run(tensors); +} +} /* namespace experimental */ + +struct CLLogicalOr::Impl +{ + const ICLTensor *src0{ nullptr }; + const ICLTensor *src1{ nullptr }; + ICLTensor *dst{ nullptr }; + std::unique_ptr op{ nullptr }; +}; + +CLLogicalOr::CLLogicalOr() + : _impl(support::cpp14::make_unique()) +{ +} +CLLogicalOr::CLLogicalOr(CLLogicalOr &&) = default; +CLLogicalOr &CLLogicalOr::operator=(CLLogicalOr &&) = default; +CLLogicalOr::~CLLogicalOr() = default; + +void CLLogicalOr::configure(ICLTensor *input1, ICLTensor *input2, ICLTensor *output) +{ + configure(CLKernelLibrary::get().get_compile_context(), input1, input2, output); +} + +void CLLogicalOr::configure(const CLCompileContext &compile_context, ICLTensor *input1, ICLTensor *input2, ICLTensor *output) +{ + _impl->src0 = input1; + _impl->src1 = input2; + _impl->dst = output; + _impl->op = arm_compute::support::cpp14::make_unique(); + _impl->op->configure(compile_context, input1->info(), input2->info(), output->info()); +} + +Status CLLogicalOr::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output) +{ + return experimental::CLLogicalOr::validate(input1, input2, output); +} + +void CLLogicalOr::run() +{ + ITensorPack pack; + pack.add_tensor(TensorType::ACL_SRC_0, _impl->src0); + pack.add_tensor(TensorType::ACL_SRC_1, _impl->src1); + pack.add_tensor(TensorType::ACL_DST, _impl->dst); + + _impl->op->run(pack); +} +} // namespace arm_compute -- cgit v1.2.1