From 61ba0697756af0e4dc191af158669af0cee2be79 Mon Sep 17 00:00:00 2001 From: Georgios Pinitas Date: Sun, 10 Jan 2021 04:07:39 +0000 Subject: Make Concatenate kernels and operator stateless - Rename all concatenate kernels to use the Cpu prefix and move appropriately Change-Id: If647173e84969936ebd211d4d5ae6d1e73150bdc Signed-off-by: Georgios Pinitas Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4799 Comments-Addressed: Arm Jenkins Tested-by: Arm Jenkins Reviewed-by: Sang-Hoon Park Reviewed-by: Giorgio Arena --- src/runtime/cpu/operators/CpuConcatenate.h | 81 ++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 src/runtime/cpu/operators/CpuConcatenate.h (limited to 'src/runtime/cpu/operators/CpuConcatenate.h') diff --git a/src/runtime/cpu/operators/CpuConcatenate.h b/src/runtime/cpu/operators/CpuConcatenate.h new file mode 100644 index 0000000000..376534275f --- /dev/null +++ b/src/runtime/cpu/operators/CpuConcatenate.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef ARM_COMPUTE_CPU_CONCATENATE_H +#define ARM_COMPUTE_CPU_CONCATENATE_H + +#include "src/core/cpu/ICpuKernel.h" +#include "src/runtime/cpu/ICpuOperator.h" + +#include + +namespace arm_compute +{ +namespace cpu +{ +/** Basic function to execute concatenate tensors along a given axis. This function calls the following kernels: + * + * -# @ref CpuConcatenateWidthKernel (if underlying concatenation axis is 0). + * -# @ref CpuConcatenateHeightKernel (if underlying concatenation axis is 1). + * -# @ref CpuConcatenateDepthKernel (if underlying concatenation axis is 2). + * -# @ref CpuConcatenateBatchKernel (if underlying concatenation axis is 3). + */ +class CpuConcatenate : public ICpuOperator +{ +public: + /** Constructor */ + CpuConcatenate(); + /** Configure operator for a given list of arguments + * + * @note Input and output tensor dimensions preconditions defer depending on the concatenation axis. + * @note Preconditions can be found respectively at @ref CpuConcatenateWidthKernel, @ref CpuConcatenateHeightKernel, @ref CpuConcatenateDepthKernel and @ref CpuConcatenateBatchKernel. + * + * @param[in,out] srcs_vector The vectors containing all the tensors to concatenate. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. + * @param[out] dst Output tensor. Data types supported: Same as @p srcs_vector. + * @param[in] axis Concatenation axis. Supported underlying concatenation axis are 0, 1, 2 and 3. + */ + void configure(const std::vector &srcs_vector, ITensorInfo *dst, size_t axis); + /** Static function to check if given info will lead to a valid configuration of @ref NEConcatenateLayer + * + * @note Input and output tensor dimensions preconditions defer depending on the concatenation axis. + * @note Preconditions can be found respectively at @ref CpuConcatenateWidthKernel, @ref CpuConcatenateHeightKernel, @ref CpuConcatenateDepthKernel and @ref CpuConcatenateBatchKernel. + * + * @param[in] srcs_vector The vectors containing all the tensors info to concatenate. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. + * @param[in] dst Output tensor info. Data types supported: Same as @p srcs_vector. + * @param[in] axis Concatenation axis. Supported underlying concatenation axis are 0, 1, 2 and 3. + * + * @return a status + */ + static Status validate(const std::vector &srcs_vector, const ITensorInfo *dst, size_t axis); + + // Inherited methods overridden: + void run(ITensorPack &tensors) override; + +private: + std::vector> _concat_kernels; + unsigned int _num_srcs; + unsigned int _axis; +}; +} // namespace cpu +} // namespace arm_compute +#endif /* ARM_COMPUTE_CPU_CONCATENATE_H */ -- cgit v1.2.1