From 17812ba9f7cf2c8f5121c11760ac45fbbdb7aeaf Mon Sep 17 00:00:00 2001 From: Georgios Pinitas Date: Mon, 4 Jun 2018 19:27:13 +0100 Subject: COMPMID-817: Tuner: Port kernels to new design. Change-Id: Iaabb1153c2abe0400ec79d51a21347debe92d642 Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/134062 Tested-by: Jenkins Reviewed-by: Anthony Barbier --- src/runtime/CL/functions/CLPoolingLayer.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/runtime/CL/functions/CLPoolingLayer.cpp') diff --git a/src/runtime/CL/functions/CLPoolingLayer.cpp b/src/runtime/CL/functions/CLPoolingLayer.cpp index 17875a38ad..cbe1ce3b47 100644 --- a/src/runtime/CL/functions/CLPoolingLayer.cpp +++ b/src/runtime/CL/functions/CLPoolingLayer.cpp @@ -63,6 +63,9 @@ void CLPoolingLayer::configure(ICLTensor *input, ICLTensor *output, const Poolin ARM_COMPUTE_ERROR("Data layout not supported"); } _border_handler.configure(input, _kernel->border_size(), border_mode, pixel_value); + + // Tune kernels + CLScheduler::get().tune_kernel_static(*_kernel); } Status CLPoolingLayer::validate(const ITensorInfo *input, const ITensorInfo *output, const PoolingLayerInfo &pool_info) -- cgit v1.2.1