From 75eea338eb232ebdafa2fb84d22e711b5f964785 Mon Sep 17 00:00:00 2001
From: Sang-Hoon Park <sang-hoon.park@arm.com>
Date: Fri, 13 Nov 2020 13:44:13 +0000
Subject: COMPMID-3961: Add Logical OR/AND/NOT operator on CL

Change-Id: I612aeed6affa17624fb9044964dd59c41a5c9888
Signed-off-by: Sang-Hoon Park <sang-hoon.park@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4448
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
---
 src/runtime/CL/functions/CLLogicalAnd.cpp | 97 +++++++++++++++++++++++++++++++
 1 file changed, 97 insertions(+)
 create mode 100644 src/runtime/CL/functions/CLLogicalAnd.cpp

(limited to 'src/runtime/CL/functions/CLLogicalAnd.cpp')

diff --git a/src/runtime/CL/functions/CLLogicalAnd.cpp b/src/runtime/CL/functions/CLLogicalAnd.cpp
new file mode 100644
index 0000000000..55d3dc523b
--- /dev/null
+++ b/src/runtime/CL/functions/CLLogicalAnd.cpp
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2020 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "arm_compute/runtime/CL/functions/CLLogicalAnd.h"
+#include "arm_compute/core/CL/ICLTensor.h"
+#include "src/core/CL/kernels/CLElementwiseOperationKernel.h"
+#include "support/MemorySupport.h"
+
+#include <utility>
+
+namespace arm_compute
+{
+namespace experimental
+{
+void CLLogicalAnd::configure(const CLCompileContext &compile_context, ITensorInfo *input1, ITensorInfo *input2, ITensorInfo *output)
+{
+    auto k = arm_compute::support::cpp14::make_unique<CLLogicalBinaryKernel>();
+    k->configure(compile_context, kernels::LogicalOperation::And, input1, input2, output);
+    _kernel = std::move(k);
+}
+
+Status CLLogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output)
+{
+    return CLLogicalBinaryKernel::validate(kernels::LogicalOperation::And, input1, input2, output);
+}
+
+void CLLogicalAnd::run(ITensorPack &tensors)
+{
+    ICLOperator::run(tensors);
+}
+} // namespace experimental
+
+struct CLLogicalAnd::Impl
+{
+    const ICLTensor                            *src0{ nullptr };
+    const ICLTensor                            *src1{ nullptr };
+    ICLTensor                                  *dst{ nullptr };
+    std::unique_ptr<experimental::CLLogicalAnd> op{ nullptr };
+};
+
+CLLogicalAnd::CLLogicalAnd()
+    : _impl(support::cpp14::make_unique<Impl>())
+{
+}
+CLLogicalAnd::CLLogicalAnd(CLLogicalAnd &&) = default;
+CLLogicalAnd &CLLogicalAnd::operator=(CLLogicalAnd &&) = default;
+CLLogicalAnd::~CLLogicalAnd()                          = default;
+
+void CLLogicalAnd::configure(ICLTensor *input1, ICLTensor *input2, ICLTensor *output)
+{
+    configure(CLKernelLibrary::get().get_compile_context(), input1, input2, output);
+}
+
+void CLLogicalAnd::configure(const CLCompileContext &compile_context, ICLTensor *input1, ICLTensor *input2, ICLTensor *output)
+{
+    _impl->src0 = input1;
+    _impl->src1 = input2;
+    _impl->dst  = output;
+    _impl->op   = arm_compute::support::cpp14::make_unique<experimental::CLLogicalAnd>();
+    _impl->op->configure(compile_context, input1->info(), input2->info(), output->info());
+}
+
+Status CLLogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output)
+{
+    return experimental::CLLogicalAnd::validate(input1, input2, output);
+}
+
+void CLLogicalAnd::run()
+{
+    ITensorPack pack;
+    pack.add_tensor(TensorType::ACL_SRC_0, _impl->src0);
+    pack.add_tensor(TensorType::ACL_SRC_1, _impl->src1);
+    pack.add_tensor(TensorType::ACL_DST, _impl->dst);
+
+    _impl->op->run(pack);
+}
+} // namespace arm_compute
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