From df6a3b05842a98702437347ca269138ccd55f852 Mon Sep 17 00:00:00 2001 From: Ramy Elgammal Date: Wed, 30 Nov 2022 16:23:10 +0000 Subject: Use heuristics for setting dynamic fusion direct conv2d tile sizes Resolves: COMPMID-5735 Change-Id: I9958413b69c5052cfa205dd0e9457cc4953aaf35 Signed-off-by: Ramy Elgammal Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/VisualCompute/ComputeLibrary/+/474818 Tested-by: bsgcomp Reviewed-by: Gian Marco Iodice Comments-Addressed: bsgcomp Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8724 Tested-by: Arm Jenkins Comments-Addressed: Arm Jenkins Benchmark: Arm Jenkins --- .../ClDirectConvDefaultConfigBifrost.cpp | 192 ---------- .../direct_conv/ClDirectConvDefaultConfigBifrost.h | 55 --- .../ClDirectConvDefaultConfigValhall.cpp | 400 --------------------- .../direct_conv/ClDirectConvDefaultConfigValhall.h | 55 --- .../kernels/direct_conv/ClDirectConvKernelConfig.h | 64 ---- .../direct_conv/IClDirectConvKernelConfig.h | 115 ------ src/gpu/cl/operators/ClDirectConv2d.cpp | 8 +- 7 files changed, 4 insertions(+), 885 deletions(-) delete mode 100644 src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.cpp delete mode 100644 src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.h delete mode 100644 src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.cpp delete mode 100644 src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.h delete mode 100644 src/gpu/cl/kernels/direct_conv/ClDirectConvKernelConfig.h delete mode 100644 src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h (limited to 'src/gpu/cl') diff --git a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.cpp b/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.cpp deleted file mode 100644 index ba176f8c5f..0000000000 --- a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.cpp +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#include "src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.h" - -#include "arm_compute/core/CL/CLHelpers.h" -#include "arm_compute/core/CL/CLKernelLibrary.h" -#include "arm_compute/core/GPUTarget.h" -#include "arm_compute/core/TensorInfo.h" -#include "arm_compute/core/TensorShape.h" -#include "arm_compute/core/utils/misc/ShapeCalculator.h" -#include - -namespace arm_compute -{ -namespace cl_direct_conv -{ -using namespace arm_compute::misc::shape_calculator; - -ClDirectConvDefaultConfigBifrost::ClDirectConvDefaultConfigBifrost(GPUTarget gpu) - : IClDirectConvKernelConfig(gpu) -{ -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigBifrost::configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - using ConfigurationFunctionExecutorPtr = DirectConvComputeKernelInfo (ClDirectConvDefaultConfigBifrost::*)(const ITensorInfo * src, const ITensorInfo * wei, const PadStrideInfo & conv_info); - - ClDirectConvConfigArray configs_G71(&ClDirectConvDefaultConfigBifrost::configure_G71_f32, - &ClDirectConvDefaultConfigBifrost::configure_G71_f16, - &ClDirectConvDefaultConfigBifrost::configure_G71_u8); - - ClDirectConvConfigArray configs_default(&ClDirectConvDefaultConfigBifrost::configure_default_f32, - &ClDirectConvDefaultConfigBifrost::configure_default_f16, - &ClDirectConvDefaultConfigBifrost::configure_G71_u8); - - ConfigurationFunctionExecutorPtr func = nullptr; - switch(_target) - { - case GPUTarget::G71: - func = configs_G71.get_function(src->data_type()); - break; - default: - func = configs_default.get_function(src->data_type()); - break; - } - - ARM_COMPUTE_ERROR_ON_MSG(func == nullptr, "Data type not supported for direct convolution"); - return (this->*func)(src, wei, conv_info); -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigBifrost::configure_G71_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - TensorShape output_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - - desc.n0 = 4; - - if(output_shape[0] > 16) - { - desc.m0 = 2; - } - - desc.k0 = 8; - - desc.export_weights_to_cl_image = false; - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigBifrost::configure_G71_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - TensorShape output_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - - desc.n0 = 4; - - if(output_shape[0] > 16) - { - desc.m0 = 4; - } - - desc.k0 = 8; - - desc.export_weights_to_cl_image = false; - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigBifrost::configure_G71_u8(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - TensorShape output_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - - desc.n0 = 4; - - if(output_shape[0] > 16) - { - desc.m0 = 4; - } - - desc.k0 = 16; - - desc.export_weights_to_cl_image = false; - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigBifrost::configure_default_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - TensorShape output_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - - desc.n0 = 4; - - if(output_shape[0] > 16) - { - desc.m0 = 2; - } - - desc.k0 = 8; - - desc.export_weights_to_cl_image = export_to_cl_image(wei); - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigBifrost::configure_default_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - TensorShape output_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - - desc.n0 = 4; - - if(output_shape[0] > 16) - { - desc.m0 = 4; - } - - desc.k0 = 8; - - desc.export_weights_to_cl_image = export_to_cl_image(wei); - } - - return desc; -} -} // namespace opencl -} // namespace arm_compute diff --git a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.h b/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.h deleted file mode 100644 index 1e4cb66ec0..0000000000 --- a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef ARM_COMPUTE_CL_DIRECT_CONV_DEFAULT_CONFIG_BIFROST_H -#define ARM_COMPUTE_CL_DIRECT_CONV_DEFAULT_CONFIG_BIFROST_H - -#include "src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h" - -namespace arm_compute -{ -namespace cl_direct_conv -{ -/** Bifrost based OpenCL direct convolution configuration */ -class ClDirectConvDefaultConfigBifrost final : public IClDirectConvKernelConfig -{ -public: - /** Constructor - * - * @param[in] gpu GPU target - */ - ClDirectConvDefaultConfigBifrost(GPUTarget gpu); - - // Inherited overridden method - DirectConvComputeKernelInfo configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) override; - -private: - DirectConvComputeKernelInfo configure_G71_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_G71_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_G71_u8(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_default_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_default_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); -}; -} // namespace opencl -} // namespace arm_compute -#endif /* ARM_COMPUTE_CL_DIRECT_CONV_DEFAULT_CONFIG_BIFROST_H */ diff --git a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.cpp b/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.cpp deleted file mode 100644 index b693568c67..0000000000 --- a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.cpp +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#include "src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.h" - -#include "arm_compute/core/CL/CLHelpers.h" -#include "arm_compute/core/CL/CLKernelLibrary.h" -#include "arm_compute/core/GPUTarget.h" -#include "arm_compute/core/TensorInfo.h" -#include "arm_compute/core/TensorShape.h" -#include "arm_compute/core/utils/misc/ShapeCalculator.h" -#include - -namespace arm_compute -{ -namespace cl_direct_conv -{ -using namespace arm_compute::misc::shape_calculator; - -ClDirectConvDefaultConfigValhall::ClDirectConvDefaultConfigValhall(GPUTarget gpu) - : IClDirectConvKernelConfig(gpu) -{ -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigValhall::configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - using ConfigurationFunctionExecutorPtr = DirectConvComputeKernelInfo (ClDirectConvDefaultConfigValhall::*)(const ITensorInfo * src, const ITensorInfo * wei, const PadStrideInfo & conv_info); - - ClDirectConvConfigArray configs_G78(&ClDirectConvDefaultConfigValhall::configure_G78_f32, - &ClDirectConvDefaultConfigValhall::configure_G78_f16, - &ClDirectConvDefaultConfigValhall::configure_G78_u8); - - ClDirectConvConfigArray configs_G57(&ClDirectConvDefaultConfigValhall::configure_G57_f32, - &ClDirectConvDefaultConfigValhall::configure_G57_f16, - &ClDirectConvDefaultConfigValhall::configure_G78_u8); - - ConfigurationFunctionExecutorPtr func = nullptr; - switch(_target) - { - case GPUTarget::G57: - func = configs_G57.get_function(src->data_type()); - break; - case GPUTarget::G78: - default: - func = configs_G78.get_function(src->data_type()); - break; - } - - ARM_COMPUTE_ERROR_ON_MSG(func == nullptr, "Data type not supported for direct convolution"); - return (this->*func)(src, wei, conv_info); -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigValhall::configure_G78_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - const TensorShape wei_shape = wei->tensor_shape(); - const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - const bool export_weights_to_cl_image = export_to_cl_image(wei); - - const int32_t ofm = dst_shape[0]; - const int32_t m = dst_shape[1] * dst_shape[2]; - const bool is_pointwise = (wei_shape[1] == wei_shape[2]) && wei_shape[1] == 1; - - desc.export_weights_to_cl_image = export_weights_to_cl_image; - - if(dst_shape[0] <= 4) - { - if(is_pointwise) - { - if(ofm == 4) - { - desc.m0 = 1; - desc.n0 = 4; - desc.k0 = 16; - } - else - { - desc.m0 = 1; - desc.n0 = 1; - desc.k0 = 16; - } - } - else - { - desc.m0 = 1; - desc.n0 = 2; - desc.k0 = 16; - } - } - else - { - if(m < 64) - { - desc.m0 = 1; - desc.n0 = 1; - desc.k0 = 16; - } - else - { - desc.m0 = 4; - desc.n0 = 4; - desc.k0 = 4; - } - } - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigValhall::configure_G78_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - const TensorShape wei_shape = wei->tensor_shape(); - const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - const bool export_weights_to_cl_image = export_to_cl_image(wei); - - const int32_t ofm = dst_shape[0]; - const int32_t m = dst_shape[1] * dst_shape[2]; - const int32_t k = wei_shape[0]; - const bool is_pointwise = (wei_shape[1] == wei_shape[2]) && wei_shape[1] == 1; - - desc.export_weights_to_cl_image = export_weights_to_cl_image; - - if(dst_shape[0] <= 4) - { - // k0 should be as larger as possible. However, we should avoid - // having left-over for loops that make the implementation slower. - if((k % 16) == 0) - { - desc.k0 = 16; - } - else if((k % 8) == 0) - { - desc.k0 = 8; - } - else - { - desc.k0 = 4; - } - - if(is_pointwise) - { - if(ofm == 4) - { - desc.m0 = 1; - desc.n0 = 4; - } - else - { - desc.m0 = 1; - desc.n0 = 1; - } - } - else - { - desc.m0 = 1; - desc.n0 = dst_shape[0]; - } - } - else - { - if(m < 64) - { - desc.m0 = 1; - desc.n0 = 1; - if((k % 16) == 0) - { - desc.k0 = 16; - } - else if((k % 8) == 0) - { - desc.k0 = 8; - } - else - { - desc.k0 = 4; - } - } - else - { - if(ofm >= 16) - { - if(m / 6 > 24000) - { - desc.m0 = 6; - } - else - { - desc.m0 = 5; - } - desc.n0 = 8; - desc.k0 = 4; - } - else - { - desc.m0 = 2; - desc.n0 = 8; - if((k % 16) == 0) - { - desc.k0 = 16; - } - else if((k % 8) == 0) - { - desc.k0 = 8; - } - else - { - desc.k0 = 4; - } - } - } - } - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigValhall::configure_G78_u8(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - TensorShape output_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - - desc.n0 = 4; - - if(output_shape[0] > 16) - { - desc.m0 = 4; - } - - desc.k0 = 16; - - desc.export_weights_to_cl_image = false; - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigValhall::configure_G57_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - const TensorShape wei_shape = wei->tensor_shape(); - const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - const bool export_weights_to_cl_image = export_to_cl_image(wei); - - const int32_t m = dst_shape[1] * dst_shape[2]; - const bool is_pointwise = (wei_shape[1] == wei_shape[2]) && wei_shape[1] == 1; - - desc.export_weights_to_cl_image = export_weights_to_cl_image; - - if(dst_shape[0] <= 4) - { - if(is_pointwise) - { - desc.m0 = 1; - desc.n0 = 1; - desc.k0 = 16; - } - else - { - desc.m0 = 1; - desc.n0 = dst_shape[0]; - desc.k0 = 16; - } - } - else - { - if(m < 64) - { - if(m == 1) - { - desc.m0 = 1; - desc.n0 = 1; - desc.k0 = 16; - } - else - { - desc.m0 = 4; - desc.n0 = 2; - desc.k0 = 8; - } - } - else - { - desc.m0 = 4; - desc.n0 = 4; - desc.k0 = 4; - } - } - } - - return desc; -} - -DirectConvComputeKernelInfo ClDirectConvDefaultConfigValhall::configure_G57_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) -{ - DirectConvComputeKernelInfo desc; - - if(src->data_layout() == DataLayout::NHWC) - { - // Get the output shape - const TensorShape wei_shape = wei->tensor_shape(); - const TensorShape dst_shape = misc::shape_calculator::compute_deep_convolution_shape(*src, *wei, conv_info); - const bool export_weights_to_cl_image = export_to_cl_image(wei); - - const int32_t ofm = dst_shape[0]; - const int32_t m = dst_shape[1] * dst_shape[2]; - const bool is_pointwise = (wei_shape[1] == wei_shape[2]) && wei_shape[1] == 1; - - desc.export_weights_to_cl_image = export_weights_to_cl_image; - - if(dst_shape[0] <= 4) - { - if(is_pointwise) - { - desc.m0 = 2; - desc.n0 = 1; - desc.k0 = 16; - } - else - { - desc.m0 = 1; - desc.n0 = dst_shape[0]; - desc.k0 = 16; - } - } - else - { - if(m < 64) - { - if(m == 1) - { - desc.m0 = 1; - desc.n0 = 1; - desc.k0 = 16; - } - else - { - desc.m0 = 4; - desc.n0 = 2; - desc.k0 = 8; - } - } - else - { - if(ofm > 16) - { - desc.m0 = 4; - desc.n0 = 8; - desc.k0 = 8; - } - else - { - desc.m0 = 8; - desc.n0 = 4; - desc.k0 = 4; - } - } - } - } - - return desc; -} -} // namespace opencl -} // namespace arm_compute diff --git a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.h b/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.h deleted file mode 100644 index 2c65b88846..0000000000 --- a/src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef ARM_COMPUTE_CL_DIRECT_CONV_DEFAULT_CONFIG_VALHALL_H -#define ARM_COMPUTE_CL_DIRECT_CONV_DEFAULT_CONFIG_VALHALL_H - -#include "src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h" - -namespace arm_compute -{ -namespace cl_direct_conv -{ -/** Valhall based OpenCL direct convolution configuration */ -class ClDirectConvDefaultConfigValhall final : public IClDirectConvKernelConfig -{ -public: - /** Constructor - * - * @param[in] gpu GPU target - */ - ClDirectConvDefaultConfigValhall(GPUTarget gpu); - - // Inherited overridden method - DirectConvComputeKernelInfo configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) override; - -private: - DirectConvComputeKernelInfo configure_G78_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_G78_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_G78_u8(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_G57_f32(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); - DirectConvComputeKernelInfo configure_G57_f16(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info); -}; -} // namespace opencl -} // namespace arm_compute -#endif /* ARM_COMPUTE_CL_DIRECT_CONV_DEFAULT_CONFIG_VALHALL_H */ diff --git a/src/gpu/cl/kernels/direct_conv/ClDirectConvKernelConfig.h b/src/gpu/cl/kernels/direct_conv/ClDirectConvKernelConfig.h deleted file mode 100644 index c1c2e439c6..0000000000 --- a/src/gpu/cl/kernels/direct_conv/ClDirectConvKernelConfig.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef ARM_COMPUTE_CL_DIRECT_CONV_KERNEL_CONFIGURATION_H -#define ARM_COMPUTE_CL_DIRECT_CONV_KERNEL_CONFIGURATION_H - -#include "src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.h" -#include "src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.h" -#include "src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h" - -#include - -namespace arm_compute -{ -namespace cl_direct_conv -{ -/** ClDirectConvolution factory class */ -class ClDirectConvKernelConfigurationFactory final -{ -public: - /** Static method to call the ClDirectConvolution kernel configuration class accordingly with the GPU target - * - * @param[in] gpu GPU target - * - * @return IClDirectConvKernelConfig - */ - static std::unique_ptr create(GPUTarget gpu) - { - switch(get_arch_from_target(gpu)) - { - case GPUTarget::MIDGARD: - return std::make_unique(GPUTarget::G71); - case GPUTarget::BIFROST: - return std::make_unique(gpu); - case GPUTarget::VALHALL: - return std::make_unique(gpu); - default: - ARM_COMPUTE_ERROR("Not supported GPU target"); - } - } -}; -} // namespace opencl -} // namespace arm_compute -#endif /* ARM_COMPUTE_CL_DIRECT_CONV_KERNEL_CONFIGURATION_H */ diff --git a/src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h b/src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h deleted file mode 100644 index 837fa35341..0000000000 --- a/src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2022 Arm Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef ARM_COMPUTE_ICL_DIRECT_CONV_KERNEL_CONFIG_H -#define ARM_COMPUTE_ICL_DIRECT_CONV_KERNEL_CONFIG_H - -#include "arm_compute/core/GPUTarget.h" -#include "arm_compute/core/KernelDescriptors.h" -#include "arm_compute/core/Types.h" -#include "src/core/common/Macros.h" - -namespace arm_compute -{ -namespace cl_direct_conv -{ -/** Basic container for the OpenCL direct convolution configuration functions */ -template -class ClDirectConvConfigArray -{ -public: - /** Alias for F32 index */ - static constexpr size_t DT_F32 = 0; - /** Alias for F16 index */ - static constexpr size_t DT_F16 = 1; - /** Alias for Int8 index */ - static constexpr size_t DT_INT8 = 2; - - /** Constructor - * - * @param[in] func_f32 Function to call for direct convolution F32 - * @param[in] func_f16 Function to call for direct convolution F16 - * @param[in] func_int8 Function to call for direct convolution Int8 (QASYMM8, QASYMM8_SIGNED, QSYMM8_PER_CHANNEL) - * - */ - ClDirectConvConfigArray(T func_f32, T func_f16, T func_int8) - : _configs{ func_f32, func_f16, func_int8 } - { - } - - /** Method to return the direct convolution configuration function based on data type - * - * @param[in] data_type Input data type - * - * @return the valid function otherwise it returns nullptr if the data type is not valid - */ - T get_function(DataType data_type) - { - switch(data_type) - { - case DataType::F32: - return _configs.at(DT_F32); - case DataType::F16: - return _configs.at(DT_F16); - case DataType::QASYMM8: - case DataType::QASYMM8_SIGNED: - case DataType::QSYMM8_PER_CHANNEL: - return _configs.at(DT_INT8); - default: - return nullptr; - } - } - -private: - std::array _configs; -}; - -/** Basic interface for the Direct convolution kernel configuration */ -class IClDirectConvKernelConfig -{ -public: - /** Constructor - * - * @param[in] arch GPU target - */ - IClDirectConvKernelConfig(GPUTarget arch) - : _target(arch) - { - } - ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(IClDirectConvKernelConfig); - /** Virtual destructor */ - virtual ~IClDirectConvKernelConfig() = default; - /** This method returns the @ref DirectConvComputeKernelInfo for the given inputs - * - * @param[in] src Source tensor (activation tensor) - * @param[in] wei Weights tensor - * @param[in] conv_info Convolution info - */ - virtual DirectConvComputeKernelInfo configure(const ITensorInfo *src, const ITensorInfo *wei, const PadStrideInfo &conv_info) = 0; - -protected: - GPUTarget _target; -}; -} // namespace opencl -} // namespace arm_compute -#endif /* ARM_COMPUTE_ICL_DIRECT_CONV_KERNEL_CONFIG_H */ diff --git a/src/gpu/cl/operators/ClDirectConv2d.cpp b/src/gpu/cl/operators/ClDirectConv2d.cpp index ded275dbae..0215dba422 100644 --- a/src/gpu/cl/operators/ClDirectConv2d.cpp +++ b/src/gpu/cl/operators/ClDirectConv2d.cpp @@ -30,10 +30,10 @@ #include "src/core/helpers/AutoConfiguration.h" #include "src/gpu/cl/kernels/ClActivationKernel.h" #include "src/gpu/cl/kernels/ClDirectConv2dKernel.h" -#include "src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigBifrost.h" -#include "src/gpu/cl/kernels/direct_conv/ClDirectConvDefaultConfigValhall.h" -#include "src/gpu/cl/kernels/direct_conv/ClDirectConvKernelConfig.h" -#include "src/gpu/cl/kernels/direct_conv/IClDirectConvKernelConfig.h" +#include "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigBifrost.h" +#include "src/runtime/heuristics/direct_conv/ClDirectConvDefaultConfigValhall.h" +#include "src/runtime/heuristics/direct_conv/ClDirectConvKernelConfig.h" +#include "src/runtime/heuristics/direct_conv/IClDirectConvKernelConfig.h" #include "src/common/utils/Log.h" -- cgit v1.2.1