From 4cbcb840caca1346de5f2271b67e4ede17b72734 Mon Sep 17 00:00:00 2001 From: alerah01 Date: Mon, 28 Feb 2022 06:38:08 +0200 Subject: Removing SVE / SVE2 guards from decoupled kernels Jira: COMPMID-5172 Signed-off-by: alerah01 Change-Id: I1b9ace8e573f85830f29728a27adfe39a0cab113 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7241 Tested-by: Arm Jenkins Reviewed-by: Giorgio Arena Comments-Addressed: Arm Jenkins --- src/cpu/kernels/scale/sve/qasymm8_signed.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/cpu/kernels/scale/sve/qasymm8_signed.cpp') diff --git a/src/cpu/kernels/scale/sve/qasymm8_signed.cpp b/src/cpu/kernels/scale/sve/qasymm8_signed.cpp index 0843e61fd4..63f515442b 100644 --- a/src/cpu/kernels/scale/sve/qasymm8_signed.cpp +++ b/src/cpu/kernels/scale/sve/qasymm8_signed.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if defined(ARM_COMPUTE_ENABLE_SVE) + #include "arm_compute/core/Helpers.h" #include "arm_compute/core/ITensorPack.h" #include "arm_compute/core/Window.h" @@ -203,5 +203,3 @@ void qasymm8_signed_sve_scale(const ITensor *src, ITensor *dst, const ITensor *o } } // namespace cpu } // namespace arm_compute - -#endif // ARM_COMPUTE_ENABLE_SVE \ No newline at end of file -- cgit v1.2.1