From 4cbcb840caca1346de5f2271b67e4ede17b72734 Mon Sep 17 00:00:00 2001
From: alerah01 <alex.rahlis@arm.com>
Date: Mon, 28 Feb 2022 06:38:08 +0200
Subject: Removing SVE / SVE2 guards from decoupled kernels

Jira: COMPMID-5172

Signed-off-by: alerah01 <alex.rahlis@arm.com>
Change-Id: I1b9ace8e573f85830f29728a27adfe39a0cab113
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7241
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
---
 src/cpu/kernels/activation/generic/sve2/qasymm8.cpp        | 5 ++---
 src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp | 4 +---
 src/cpu/kernels/activation/generic/sve2/qsymm16.cpp        | 4 +---
 3 files changed, 4 insertions(+), 9 deletions(-)

(limited to 'src/cpu/kernels/activation/generic/sve2')

diff --git a/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp b/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp
index 3b99c0f120..de513679d5 100644
--- a/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp
+++ b/src/cpu/kernels/activation/generic/sve2/qasymm8.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021 Arm Limited.
+ * Copyright (c) 2020-2022 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -21,7 +21,7 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  */
-#if defined(ARM_COMPUTE_ENABLE_SVE2)
+
 #include "arm_compute/core/Helpers.h"
 #include "arm_compute/core/Window.h"
 
@@ -250,4 +250,3 @@ void sve2_qasymm8_activation(const ITensor *src, ITensor *dst, const ActivationL
 }
 } // namespace cpu
 } // namespace arm_compute
-#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */
\ No newline at end of file
diff --git a/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp b/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp
index 24415145d3..906ec877f9 100644
--- a/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp
+++ b/src/cpu/kernels/activation/generic/sve2/qasymm8_signed.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021 Arm Limited.
+ * Copyright (c) 2020-2022 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -28,7 +28,6 @@
 #include <cmath>
 #include <cstddef>
 
-#if defined(ARM_COMPUTE_ENABLE_SVE2)
 #include "src/core/NEON/SVEAsymm.h"
 #include "src/core/NEON/SVEMath.h"
 #include <arm_sve.h>
@@ -250,4 +249,3 @@ void sve2_qasymm8_signed_activation(const ITensor *src, ITensor *dst, const Acti
 }
 } // namespace cpu
 } // namespace arm_compute
-#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */
diff --git a/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp b/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp
index 0eecfa618f..41b5555448 100644
--- a/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp
+++ b/src/cpu/kernels/activation/generic/sve2/qsymm16.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021 Arm Limited.
+ * Copyright (c) 2020-2022 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -29,7 +29,6 @@
 #include <cmath>
 #include <cstddef>
 
-#if defined(ARM_COMPUTE_ENABLE_SVE2)
 #include "src/core/NEON/SVEMath.h"
 #include "src/core/NEON/SVESymm.h"
 #include <arm_sve.h>
@@ -117,4 +116,3 @@ void sve2_qsymm16_activation(const ITensor *src, ITensor *dst, const ActivationL
 }
 } // namespace cpu
 } // namespace arm_compute
-#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */
-- 
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