From ac6499a474503dfcf587d95b85823aeb5861103f Mon Sep 17 00:00:00 2001 From: Sheri Zhang Date: Wed, 10 Feb 2021 15:32:38 +0000 Subject: Comply with Trademark rules for use of Neon, Arm and Mali Full trademarks available in README.md Resolves: COMPMID-4257 Signed-off-by: Sheri Zhang Change-Id: Ibfba2adf2eef3449433f467464ebd87d7198474d Signed-off-by: Michele Di Giorgio Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5116 Reviewed-by: Georgios Pinitas Comments-Addressed: Arm Jenkins Tested-by: Arm Jenkins --- src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp | 2 +- src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp | 2 +- src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp | 2 +- src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp | 2 +- src/core/cpu/kernels/CpuReshapeKernel.cpp | 2 +- src/core/cpu/kernels/activation/NEON/fp16.cpp | 4 ++-- src/core/cpu/kernels/activation/NEON/fp32.cpp | 2 +- src/core/cpu/kernels/add/neon/list.h | 4 ++-- src/core/cpu/kernels/pooling/neon/quantized.h | 8 ++++---- src/core/cpu/kernels/softmax/impl/NEON/list.h | 4 ++-- src/core/cpu/kernels/sub/neon/list.h | 4 ++-- 11 files changed, 18 insertions(+), 18 deletions(-) (limited to 'src/core/cpu/kernels') diff --git a/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp b/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp index e51c341851..48eac13041 100644 --- a/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp +++ b/src/core/cpu/kernels/CpuConcatenateBatchKernel.cpp @@ -133,7 +133,7 @@ void batch_concat(const ITensor *src, ITensor *dst, unsigned int batch_offset, c Status validate_arguments(const ITensorInfo *src, unsigned int batch_offset, const ITensorInfo *dst) { ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst); - //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions. + //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions. ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN); ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst); diff --git a/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp b/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp index dee0283a2c..f64c282ae4 100644 --- a/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp +++ b/src/core/cpu/kernels/CpuConcatenateDepthKernel.cpp @@ -134,7 +134,7 @@ void depth_concat(const ITensor *src, ITensor *dst, unsigned int depth_offset, c Status validate_arguments(const ITensorInfo *input, unsigned int depth_offset, const ITensorInfo *output) { ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output); - //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use NEON FP16 instructions. + //Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(input) is not needed here as this kernel doesn't use Neon FP16 instructions. ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(input, 1, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::F16, DataType::F32); ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(input, output); diff --git a/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp b/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp index 8522c93340..c6e224970a 100644 --- a/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp +++ b/src/core/cpu/kernels/CpuConcatenateHeightKernel.cpp @@ -49,7 +49,7 @@ namespace Status validate_arguments(const ITensorInfo *src, unsigned int height_offset, const ITensorInfo *dst) { ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst); - // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions. + // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions. ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN); ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst); ARM_COMPUTE_RETURN_ERROR_ON(src->dimension(Window::DimX) != dst->dimension(Window::DimX)); diff --git a/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp b/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp index 27ded05aff..e707e8d5a4 100644 --- a/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp +++ b/src/core/cpu/kernels/CpuConcatenateWidthKernel.cpp @@ -49,7 +49,7 @@ namespace Status validate_arguments(const ITensorInfo *src, unsigned int width_offset, const ITensorInfo *dst) { ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst); - // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions. + // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions. ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN); ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst); ARM_COMPUTE_RETURN_ERROR_ON(src->dimension(0) + width_offset > dst->dimension(0)); diff --git a/src/core/cpu/kernels/CpuReshapeKernel.cpp b/src/core/cpu/kernels/CpuReshapeKernel.cpp index 068f5d025b..41ff8bd390 100644 --- a/src/core/cpu/kernels/CpuReshapeKernel.cpp +++ b/src/core/cpu/kernels/CpuReshapeKernel.cpp @@ -50,7 +50,7 @@ namespace Status validate_arguments(const ITensorInfo *src, const ITensorInfo *dst) { ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src, dst); - // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use NEON FP16 instructions. + // Note: ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src) is not needed here as this kernel doesn't use Neon FP16 instructions. ARM_COMPUTE_RETURN_ERROR_ON(src->data_type() == DataType::UNKNOWN); ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src, dst); diff --git a/src/core/cpu/kernels/activation/NEON/fp16.cpp b/src/core/cpu/kernels/activation/NEON/fp16.cpp index bd459e9e77..7fe4ab3f63 100644 --- a/src/core/cpu/kernels/activation/NEON/fp16.cpp +++ b/src/core/cpu/kernels/activation/NEON/fp16.cpp @@ -51,7 +51,7 @@ inline float16x8_t mask_float_vector(const float16x8_t &in, const uint16x8_t &ma void fp16_neon_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window) { - /** NEON vector tag type. */ + /** Neon vector tag type. */ using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t; const ActivationLayerInfo::ActivationFunction act = act_info.activation(); @@ -215,4 +215,4 @@ void fp16_neon_activation(const ITensor *src, ITensor *dst, const ActivationLaye } // namespace cpu } // namespace arm_compute -#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ \ No newline at end of file +#endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ diff --git a/src/core/cpu/kernels/activation/NEON/fp32.cpp b/src/core/cpu/kernels/activation/NEON/fp32.cpp index c76035b5d2..f1f2753813 100644 --- a/src/core/cpu/kernels/activation/NEON/fp32.cpp +++ b/src/core/cpu/kernels/activation/NEON/fp32.cpp @@ -49,7 +49,7 @@ inline float32x4_t mask_float_vector(const float32x4_t &in, const uint32x4_t &ma void fp32_neon_activation(const ITensor *src, ITensor *dst, const ActivationLayerInfo &act_info, const Window &window) { - /** NEON vector tag type. */ + /** Neon vector tag type. */ using ExactTagType = typename arm_compute::wrapper::traits::neon_bitvector_tag_t; constexpr int window_step_x = 4; diff --git a/src/core/cpu/kernels/add/neon/list.h b/src/core/cpu/kernels/add/neon/list.h index 53ea81e284..964bdccca3 100644 --- a/src/core/cpu/kernels/add/neon/list.h +++ b/src/core/cpu/kernels/add/neon/list.h @@ -47,7 +47,7 @@ DECLARE_ADD_KERNEL(add_u8_u8_s16_neon); template void add_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window) { - /** NEON vector tag type. */ + /** Neon vector tag type. */ using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t; // Create input windows @@ -143,4 +143,4 @@ void add_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const } } // namespace cpu } // namespace arm_compute -#endif // SRC_CORE_NEON_KERNELS_ADD_LIST_H \ No newline at end of file +#endif // SRC_CORE_NEON_KERNELS_ADD_LIST_H diff --git a/src/core/cpu/kernels/pooling/neon/quantized.h b/src/core/cpu/kernels/pooling/neon/quantized.h index 81fb777ef2..535fb53d87 100644 --- a/src/core/cpu/kernels/pooling/neon/quantized.h +++ b/src/core/cpu/kernels/pooling/neon/quantized.h @@ -473,7 +473,7 @@ void pooling2_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor *ds Iterator in(src, window_src); Iterator out(dst0, window); - /** NEON vector types */ + /** Neon vector types */ using q8x8_t = typename wrapper::traits::neon_vector::type; using q8x16_t = typename wrapper::traits::neon_vector::type; using q8x8x2_t = typename std::conditional::value, uint8x8x2_t, int8x8x2_t>::type; @@ -602,7 +602,7 @@ void pooling3_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor *ds Iterator in(src, window_src); Iterator out(dst0, window); - /** NEON vector types */ + /** Neon vector types */ using q8x8_t = typename wrapper::traits::neon_vector::type; using q8x16_t = typename wrapper::traits::neon_vector::type; using q8x8x2_t = typename std::conditional::value, uint8x8x2_t, int8x8x2_t>::type; @@ -756,7 +756,7 @@ void poolingMxN_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor * Iterator in(src, window_src); Iterator out(dst0, window); - /** NEON vector types */ + /** Neon vector types */ using q8x8_t = typename wrapper::traits::neon_vector::type; using q16_t = typename wrapper::traits::promote_t; using q16x8_t = typename wrapper::traits::neon_vector::type; @@ -860,4 +860,4 @@ void poolingMxN_quantized_neon_nchw(const ITensor *src, ITensor *dst0, ITensor * } // namespace cpu } // namespace arm_compute -#endif // SRC_CORE_NEON_KERNELS_QUANTIZED_H \ No newline at end of file +#endif // SRC_CORE_NEON_KERNELS_QUANTIZED_H diff --git a/src/core/cpu/kernels/softmax/impl/NEON/list.h b/src/core/cpu/kernels/softmax/impl/NEON/list.h index 1aa7e8fac7..3f9438e0c7 100644 --- a/src/core/cpu/kernels/softmax/impl/NEON/list.h +++ b/src/core/cpu/kernels/softmax/impl/NEON/list.h @@ -73,7 +73,7 @@ float32x4x4_t convert_int_to_float(const int8x16_t &in template void neon_logits_1d_max(const ITensor *in, ITensor *out, const Window &window) { - /** NEON vector tag type. */ + /** Neon vector tag type. */ using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t; constexpr int window_step_x = 16 / sizeof(T); @@ -304,7 +304,7 @@ void neon_softmax_logits_1d_float(const ITensor *in, const ITensor *max, void *c Iterator max_it(max, window); Iterator out_it(out, window); - /** NEON vector tag type. */ + /** Neon vector tag type. */ using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t; constexpr int vec_size = 16 / sizeof(T); diff --git a/src/core/cpu/kernels/sub/neon/list.h b/src/core/cpu/kernels/sub/neon/list.h index d5685824fc..8c82402513 100644 --- a/src/core/cpu/kernels/sub/neon/list.h +++ b/src/core/cpu/kernels/sub/neon/list.h @@ -47,7 +47,7 @@ DECLARE_SUB_KERNEL(sub_u8_u8_s16_neon); template void sub_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const ConvertPolicy &policy, const Window &window) { - /** NEON vector tag type. */ + /** Neon vector tag type. */ using ExactTagType = typename wrapper::traits::neon_bitvector_tag_t; bool is_sat = policy == ConvertPolicy::SATURATE; @@ -159,4 +159,4 @@ void sub_same_neon(const ITensor *src0, const ITensor *src1, ITensor *dst, const } } // namespace cpu } // namespace arm_compute -#endif // SRC_CORE_NEON_KERNELS_SUB_LIST_H \ No newline at end of file +#endif // SRC_CORE_NEON_KERNELS_SUB_LIST_H -- cgit v1.2.1