From a2561f0ff2bdd3fd7d968a56a19c35a59804b992 Mon Sep 17 00:00:00 2001 From: "ramy.elgammal@arm.com" Date: Fri, 16 Jun 2023 20:45:48 +0100 Subject: Fix doxygen warnings Resolves: COMPMID-6312 Signed-off-by: ramy.elgammal@arm.com Change-Id: I9f68ccd2edb8c4d03fec19e6b9c29609d4833342 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9806 Tested-by: Arm Jenkins Reviewed-by: Gunes Bayir Comments-Addressed: Arm Jenkins Benchmark: Arm Jenkins --- src/core/NEON/NEAsymm.h | 11 ++++------- .../kernels/arm_conv/depthwise/depthwise_implementation.hpp | 5 ++++- .../NEON/kernels/arm_conv/pooling/pooling_implementation.hpp | 5 ++++- 3 files changed, 12 insertions(+), 9 deletions(-) (limited to 'src/core/NEON') diff --git a/src/core/NEON/NEAsymm.h b/src/core/NEON/NEAsymm.h index 5b8d2be04b..e6d0e532c8 100644 --- a/src/core/NEON/NEAsymm.h +++ b/src/core/NEON/NEAsymm.h @@ -52,7 +52,8 @@ using qasymm8x16_signed_t = int8x16_t; /**< 8 bit quantized signed asymmetric * * @return A 16-component vector in QASYMM8 format, saturated to fit */ -uint8x16_t vmlaq_qasymm8(qasymm8x16_t vd, float32x4_t vs, float32x4_t vo); +template +qasymm8x16_t vmlaq_qasymm8(qasymm8x16_t vd, float32x4_t vs, float32x4_t vo); /** Perform a multiply-accumulate on all 16 components of a QASYMM8_SIGNED vector * @@ -64,7 +65,8 @@ uint8x16_t vmlaq_qasymm8(qasymm8x16_t vd, float32x4_t vs, float32x4_t vo); * * @return A 16-component vector in QASYMM8_SIGNED format, saturated to fit */ -int8x16_t vmlaq_qasymm8_signed(qasymm8x16_signed_t vd, float32x4_t vs, float32x4_t vo); +template +qasymm8x16_signed_t vmlaq_qasymm8_signed(qasymm8x16_signed_t vd, float32x4_t vs, float32x4_t vo); /** Performs final quantization step on 16 elements * @@ -716,11 +718,6 @@ inline uint16x8x2_t vquantize_qasymm16(const float32x4x4_t &qv, const UniformQua return { pa, pb }; } -template -qasymm8x16_signed_t vmlaq_qasymm8(qasymm8x16_signed_t vd, float32x4_t vs, float32x4_t vo); - -template -qasymm8x16_signed_t vmlaq_qasymm8_signed(qasymm8x16_signed_t vd, float32x4_t vs, float32x4_t vo); } // namespace arm_compute #include "src/core/NEON/NEAsymm.inl" #endif // ARM_COMPUTE_NEASYMM_H diff --git a/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation.hpp b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation.hpp index 0f91fe363c..82821af1e6 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -61,6 +61,9 @@ struct DepthwiseImplementation } }; +/** + * \relates DepthwiseImplementation + */ template const DepthwiseImplementation *depthwise_implementation_list(); diff --git a/src/core/NEON/kernels/arm_conv/pooling/pooling_implementation.hpp b/src/core/NEON/kernels/arm_conv/pooling/pooling_implementation.hpp index 78320cec44..235aa1b635 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/pooling_implementation.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/pooling_implementation.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -57,6 +57,9 @@ struct PoolingImplementation } }; +/** + * \relates PoolingImplementation + */ template const PoolingImplementation *pooling_implementation_list(); -- cgit v1.2.1