From 7976f082599cfadeb93b00d6f99f6b6e0ab570d7 Mon Sep 17 00:00:00 2001 From: Pablo Marquez Tello Date: Tue, 13 Feb 2024 13:56:15 +0000 Subject: Fix compiler errors in cl-clang * cl-clang is used to build ACL natively in WoA * Resolves MLCE-1209 Change-Id: I040e84f526f16324138a074badf764ac099090e3 Signed-off-by: Pablo Marquez Tello Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/11126 Comments-Addressed: Arm Jenkins Reviewed-by: Jakub Sujak Tested-by: Arm Jenkins Benchmark: Arm Jenkins --- .../a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp | 4 ++-- .../a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp | 14 ++++++++++++-- .../a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp | 15 +++++++++++++-- .../a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp | 4 ++-- .../a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp | 4 ++-- .../a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp | 15 +++++++++++++-- .../a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp | 13 +++++++++++-- .../winograd/input_transforms/arm_fp32_1x8.cpp | 8 ++++---- .../winograd/output_transforms/a64_fp16_4x4_3x3.cpp | 12 ++++++------ .../winograd/output_transforms/arm_fp32_1x2_1x7.cpp | 10 +++++----- .../winograd/output_transforms/arm_fp32_1x4_1x5.cpp | 10 +++++----- .../winograd/output_transforms/arm_fp32_1x6_1x3.cpp | 10 +++++----- .../winograd/output_transforms/arm_fp32_2x2_3x3.cpp | 12 ++++++------ .../winograd/output_transforms/arm_fp32_2x2_5x5.cpp | 12 ++++++------ .../winograd/output_transforms/arm_fp32_4x4_3x3.cpp | 12 ++++++------ .../winograd/output_transforms/sme_fp32_mopa_4x4_3x3.cpp | 14 +++++++------- 24 files changed, 193 insertions(+), 80 deletions(-) (limited to 'src/core/NEON/kernels') diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp index 2b97ad816a..e51031ccdb 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,7 @@ namespace arm_conv { namespace depthwise { -void a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst_impl(unsigned int, const int8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32&, const int32_t *, const int32_t *, int8_t *const *); +void a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst_impl(const unsigned int, const int8_t *const *const, const int8_t *, const int32_t *, const arm_gemm::Requantize32&, const int32_t *, const int32_t *, int8_t *const *const); class a64_s8q_nhwc_3x3_s1_output2x2_dot_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp index a679b02f7c..874b18c145 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl(unsigned int, const int8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, int8_t *const *); +void a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const int8_t *const *const, + const int8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + int8_t *const *const +); class a64_s8q_nhwc_3x3_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp index 7370f89699..893260362a 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,17 @@ namespace arm_conv { namespace depthwise { -void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(unsigned int, const int8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, int8_t *const *); +void a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( + const unsigned int, + const int8_t *const *const, + const int8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + int8_t *const *const +); + class a64_s8q_nhwc_3x3_s2_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp index 65ebe627ef..ccab35ce57 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,18 @@ namespace arm_conv { namespace depthwise { -void a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl(unsigned int, const int8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, int8_t *const *); +void a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const int8_t *const *const, + const int8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + int8_t *const *const +); + + class a64_s8q_nhwc_5x5_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp index bd2941b3d6..3190cbfbf0 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,7 @@ namespace arm_conv { namespace depthwise { -void a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst_impl(unsigned int, const int8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32&, const int32_t *, const int32_t *, int8_t *const *); +void a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst_impl(const unsigned int , const int8_t *const *const , const int8_t *, const int32_t *, const arm_gemm::Requantize32& , const int32_t *, const int32_t *, int8_t *const *const ); class a64_s8qs_nhwc_3x3_s1_output2x2_dot_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp index ed24f8fa3c..4026855617 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,7 @@ namespace arm_conv { namespace depthwise { -void a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst_impl(unsigned int, const uint8_t *const *, const uint8_t *, const int32_t *, const arm_gemm::Requantize32&, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst_impl(const unsigned int, const uint8_t *const *const, const uint8_t *, const int32_t *, const arm_gemm::Requantize32&, const int32_t *, const int32_t *, uint8_t *const *const); class a64_u8q_nhwc_3x3_s1_output2x2_dot_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp index 9fc6a5bc34..5ae0be1054 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const uint8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const uint8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8q_nhwc_3x3_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp index f4f2bc82e1..52280ebe70 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const uint8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const uint8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8q_nhwc_3x3_s2_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp index 375e6f8f15..07f66fb482 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const uint8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const uint8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8q_nhwc_5x5_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp index 20a37b157f..db73c88187 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const uint8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const uint8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8qa_nhwc_3x3_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp index 50778e9cbb..9b646bc4f6 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const uint8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const uint8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp index f2ab5831d8..39601fd8e4 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const uint8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const uint8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8qa_nhwc_5x5_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp index 7b0b414517..1666c17ca0 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const int8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp index 5d6fbac4bd..7c05b36f36 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,18 @@ namespace arm_conv { namespace depthwise { -void a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); + + +void a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const int8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8s8u8q_nhwc_3x3_s2_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp index 32117ad1e6..5d53b17e53 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 Arm Limited. + * Copyright (c) 2021-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,7 +34,16 @@ namespace arm_conv { namespace depthwise { -void a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl(unsigned int, const uint8_t *const *, const int8_t *, const int32_t *, const arm_gemm::Requantize32 &, const int32_t *, const int32_t *, uint8_t *const *); +void a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst_impl( + const unsigned int, + const uint8_t *const *const, + const int8_t *const, + const int32_t *const, + const arm_gemm::Requantize32 &, + const int32_t *const, + const int32_t *const, + uint8_t *const *const +); class a64_u8s8u8q_nhwc_5x5_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy { diff --git a/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp b/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp index ae589f9772..3e1fc491f1 100644 --- a/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp +++ b/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -31,11 +31,11 @@ namespace input_transform { void arm_fp32_1x8( const unsigned int n_channels, - const float *const input_base, + const float * input_base, size_t, // We don't need to stride over rows - const size_t input_col_stride, + size_t input_col_stride, float *outptr, - const size_t matrix_stride + size_t matrix_stride ) { constexpr int inner_tile_cols = 8; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/a64_fp16_4x4_3x3.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/a64_fp16_4x4_3x3.cpp index 8a2837a125..295005a2ee 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/a64_fp16_4x4_3x3.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/a64_fp16_4x4_3x3.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022, 2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,13 +34,13 @@ namespace output_transform { void a64_fp16_4x4_3x3( unsigned int n_channels, const __fp16* inptr, - const size_t matrix_stride, + size_t matrix_stride, const __fp16* bptr, __fp16* const output, - const size_t output_row_stride, - const size_t output_col_stride, - const __fp16 output_min, - const __fp16 output_max + size_t output_row_stride, + size_t output_col_stride, + __fp16 output_min, + __fp16 output_max ) { constexpr int output_tile_rows = 4, output_tile_cols = 4; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x2_1x7.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x2_1x7.cpp index cce3745c77..8c6cf9725e 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x2_1x7.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x2_1x7.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,13 +33,13 @@ namespace output_transform { void arm_fp32_1x2_1x7( unsigned int n_channels, const float* inptr, - const size_t matrix_stride, + size_t matrix_stride, const float* bptr, float *outptr, size_t, // No need to stride across rows - const size_t output_col_stride, - const float output_min, - const float output_max + size_t output_col_stride, + float output_min, + float output_max ) { constexpr auto inner_tile_cols = 8u, output_tile_cols = 2u; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x4_1x5.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x4_1x5.cpp index 10f25a4aab..ac05f23221 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x4_1x5.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x4_1x5.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,13 +33,13 @@ namespace output_transform { void arm_fp32_1x4_1x5( unsigned int n_channels, const float* inptr, - const size_t matrix_stride, + size_t matrix_stride, const float* bptr, float *outptr, size_t, // No need to stride across rows - const size_t output_col_stride, - const float output_min, - const float output_max + size_t output_col_stride, + float output_min, + float output_max ) { constexpr auto inner_tile_cols = 8u, output_tile_cols = 4u; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x6_1x3.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x6_1x3.cpp index c45ff8cf2c..154dc6fe1a 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x6_1x3.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_1x6_1x3.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -34,13 +34,13 @@ namespace output_transform { void arm_fp32_1x6_1x3( unsigned int n_channels, const float* inptr, - const size_t matrix_stride, + size_t matrix_stride, const float* bptr, float *outptr, size_t, // No need to stride across rows - const size_t output_col_stride, - const float output_min, - const float output_max + size_t output_col_stride, + float output_min, + float output_max ) { constexpr unsigned int inner_tile_cols = 8, output_tile_cols = 6; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_3x3.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_3x3.cpp index 7f6b838ed8..28f042bcbf 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_3x3.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_3x3.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022, 2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,13 +33,13 @@ namespace output_transform { void arm_fp32_2x2_3x3( unsigned int n_channels, const float* inptr, - const size_t matrix_stride, + size_t matrix_stride, const float* bptr, float *outptr, - const size_t output_row_stride, - const size_t output_col_stride, - const float output_min, - const float output_max + size_t output_row_stride, + size_t output_col_stride, + float output_min, + float output_max ) { constexpr auto output_tile_rows = 2u, output_tile_cols = 2u; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_5x5.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_5x5.cpp index 0dc4851084..8e5ba74ac3 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_5x5.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_2x2_5x5.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022, 2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,13 +33,13 @@ namespace output_transform { void arm_fp32_2x2_5x5( unsigned int n_channels, const float* inptr, - const size_t matrix_stride, + size_t matrix_stride, const float* bptr, float *outptr, - const size_t output_row_stride, - const size_t output_col_stride, - const float output_min, - const float output_max + size_t output_row_stride, + size_t output_col_stride, + float output_min, + float output_max ) { constexpr auto output_tile_rows = 2u, output_tile_cols = 2u; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_4x4_3x3.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_4x4_3x3.cpp index a26fbfbf5a..72c43019fa 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_4x4_3x3.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/arm_fp32_4x4_3x3.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022, 2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,13 +33,13 @@ namespace output_transform { void arm_fp32_4x4_3x3( unsigned int n_channels, const float* inptr, - const size_t matrix_stride, + size_t matrix_stride, const float* bptr, float *outptr, - const size_t output_row_stride, - const size_t output_col_stride, - const float output_min, - const float output_max + size_t output_row_stride, + size_t output_col_stride, + float output_min, + float output_max ) { constexpr auto output_tile_rows = 4u, output_tile_cols = 4u; diff --git a/src/core/NEON/kernels/convolution/winograd/output_transforms/sme_fp32_mopa_4x4_3x3.cpp b/src/core/NEON/kernels/convolution/winograd/output_transforms/sme_fp32_mopa_4x4_3x3.cpp index 55ed24cd74..043914d590 100644 --- a/src/core/NEON/kernels/convolution/winograd/output_transforms/sme_fp32_mopa_4x4_3x3.cpp +++ b/src/core/NEON/kernels/convolution/winograd/output_transforms/sme_fp32_mopa_4x4_3x3.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -31,15 +31,15 @@ namespace winograd { namespace output_transform { void sme_fp32_mopa_4x4_3x3( - const unsigned int n_channels, + unsigned int n_channels, const float* inptr, - const size_t matrix_stride, + size_t matrix_stride, const float* bptr, float* const output, - const size_t output_row_stride, - const size_t output_col_stride, - const float output_min, - const float output_max + size_t output_row_stride, + size_t output_col_stride, + float output_min, + float output_max ) { // The below assembler uses the Kronecker product and the "vec trick" to -- cgit v1.2.1