From ce8f60510210efc0cf1c921fac75efc49bc70edc Mon Sep 17 00:00:00 2001 From: David Mansell Date: Thu, 17 May 2018 18:51:26 +0100 Subject: COMPMID-1177: Improved native GEMM. Improve the native GEMM so it can cope with any value for M. Also change the selection code so that the native GEMM is selected if M is small and nmulti is large - Winograd needs GEMMs like this and they don't thread properly with the blocked GEMM. (also rename gemm_batched.hpp back to gemv_batched.hpp) Change-Id: I736c33373ada562cbc0c00540520a58103faa9d5 Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/131739 Tested-by: Jenkins Reviewed-by: Pablo Tello Reviewed-by: Anthony Barbier --- src/core/NEON/kernels/arm_gemm/gemm_batched.hpp | 106 ------------ src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp | 24 ++- src/core/NEON/kernels/arm_gemm/gemv_batched.hpp | 110 ++++++++++++ .../kernels/a64_sgemm_native_16x4/generic.cpp | 185 ++++++++++++--------- 4 files changed, 224 insertions(+), 201 deletions(-) delete mode 100644 src/core/NEON/kernels/arm_gemm/gemm_batched.hpp create mode 100644 src/core/NEON/kernels/arm_gemm/gemv_batched.hpp (limited to 'src/core/NEON/kernels/arm_gemm') diff --git a/src/core/NEON/kernels/arm_gemm/gemm_batched.hpp b/src/core/NEON/kernels/arm_gemm/gemm_batched.hpp deleted file mode 100644 index 385358f615..0000000000 --- a/src/core/NEON/kernels/arm_gemm/gemm_batched.hpp +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2017-2018 ARM Limited. - * - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#pragma once - -#include "arm_gemm.hpp" - -namespace arm_gemm -{ -template -class GemmBatched : public GemmCommon -{ -private: - UniqueGemmCommon _subgemm = nullptr; - -public: - GemmBatched(const CPUInfo &ci, const unsigned int M, const unsigned int N, const unsigned int K, - const unsigned int nbatches, const unsigned int nmulti, const bool trA, const bool trB, - const To alpha, const To beta, const int maxthreads, const bool pretransposed_hint) - { - /* Just create a subgemm with batches->M */ - _subgemm = gemm(ci, nbatches, N, K, 1, nmulti, trA, trB, alpha, beta, maxthreads, pretransposed_hint); - } - - void set_arrays(const To *A, const int lda, const int A_batch_stride, const int A_multi_stride, - const To *B, const int ldb, const int B_multi_stride, - Tr *C, const int ldc, const int C_batch_stride, const int C_multi_stride) override - { - /* A and C's batch stride becomes their new row stride. New batch stride is 0 as nbatches for subgemm is always 1. */ - _subgemm->set_arrays(A, A_batch_stride, 0, A_multi_stride, - B, ldb, B_multi_stride, - C, C_batch_stride, 0, C_multi_stride); - } - - unsigned int get_window_size() const override - { - return _subgemm->get_window_size(); - } - - void set_nthreads(int nthreads) override - { - _subgemm->set_nthreads(nthreads); - } - - void execute(unsigned int start, unsigned int end, int threadid) override - { - _subgemm->execute(start, end, threadid); - } - - size_t get_working_size() const override - { - return _subgemm->get_working_size(); - } - - void set_working_space(void *space) override - { - _subgemm->set_working_space(space); - } - - bool B_is_pretransposed() const override - { - return _subgemm->B_is_pretransposed(); - } - - bool B_pretranspose_required() const override - { - return _subgemm->B_pretranspose_required(); - } - - size_t get_B_pretransposed_array_size() const override - { - return _subgemm->get_B_pretransposed_array_size(); - } - - void pretranspose_B_array(void *buffer, const To *B, const int ldb, const int B_multi_stride) override - { - _subgemm->pretranspose_B_array(buffer, B, ldb, B_multi_stride); - } - - void set_pretransposed_B_data(void *buffer) override - { - _subgemm->set_pretransposed_B_data(buffer); - } -}; - -} // namespace arm_gemm diff --git a/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp b/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp index 43df1aa779..c093761614 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_fp32.cpp @@ -22,10 +22,10 @@ * SOFTWARE. */ #include "arm_gemm.hpp" -#include "gemm_batched.hpp" #include "gemm_common.hpp" #include "gemm_interleaved.hpp" #include "gemm_native.hpp" +#include "gemv_batched.hpp" #include "gemv_native_transposed.hpp" #include "gemv_pretransposed.hpp" @@ -41,12 +41,10 @@ template <> UniqueGemmCommon gemm(const CPUInfo &ci, const unsigned int M, const unsigned int N, const unsigned int K, const unsigned int nbatches, const unsigned int nmulti, const bool trA, const bool trB, const float alpha, const float beta, - const int maxthreads, const bool pretransposed_hint) -{ - /* Handle "batched GEMM" */ - if(M == 1 && nbatches > 1) - { - return UniqueGemmCommon(new GemmBatched(ci, M, N, K, nbatches, nmulti, trA, trB, alpha, beta, maxthreads, pretransposed_hint)); + const int maxthreads, const bool pretransposed_hint) { + /* Handle "batched GEMV" */ + if (M==1 && nbatches>1) { + return UniqueGemmCommon (new GemvBatched(ci, M, N, K, nbatches, nmulti, trA, trB, alpha, beta, maxthreads, pretransposed_hint)); } #ifdef __aarch64__ /* Cases in priority order */ @@ -62,12 +60,12 @@ UniqueGemmCommon gemm(const CPUInfo &ci, const unsig return UniqueGemmCommon(new GemvNativeTransposed(&ci, N, K, nmulti, beta)); } - /* Native GEMM: requires M to be a multiple of 4, K at least 4, N a - * multiple of 16, doesn't handle alpha and only makes sense for small - * sizes. */ - if(N <= 128 && K <= 128 && ((M % 4) == 0) && (K >= 4) && ((N % 16) == 0) && alpha == 1.0f) - { - return UniqueGemmCommon(new GemmNative(&ci, M, N, K, nbatches, nmulti, beta)); + /* Native GEMM: requires K at least 4, N a multiple of 16, doesn't + * handle alpha or transpose. Use for small N/K, or if the blocked GEMM + * won't thread properly. */ + if ((K >= 4) && ((N % 16) == 0) && alpha==1.0f && !trA && !trB && + ((K <= 128 && N <= 128) || (nmulti > 1 && (M/maxthreads) < 8))) { + return UniqueGemmCommon (new GemmNative(&ci, M, N, K, nbatches, nmulti, beta)); } /* Blocked GEMM, handles all cases. */ diff --git a/src/core/NEON/kernels/arm_gemm/gemv_batched.hpp b/src/core/NEON/kernels/arm_gemm/gemv_batched.hpp new file mode 100644 index 0000000000..bb09770efc --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/gemv_batched.hpp @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2017-2018 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#pragma once + +#include "arm_gemm.hpp" + +namespace arm_gemm +{ + +/* "Batched GEMV" (where M=1 and nbatches>1) can be executed much more + * efficiently as a GEMM (with M'=nbatches and nbatches'=1). This wrapper + * implements this. */ +template +class GemvBatched : public GemmCommon +{ +private: + UniqueGemmCommon _subgemm = nullptr; + +public: + GemvBatched(const CPUInfo &ci, const unsigned int M, const unsigned int N, const unsigned int K, + const unsigned int nbatches, const unsigned int nmulti, const bool trA, const bool trB, + const To alpha, const To beta, const int maxthreads, const bool pretransposed_hint) + { + /* Just create a subgemm with batches->M */ + _subgemm = gemm(ci, nbatches, N, K, 1, nmulti, trA, trB, alpha, beta, maxthreads, pretransposed_hint); + } + + void set_arrays(const To *A, const int lda, const int A_batch_stride, const int A_multi_stride, + const To *B, const int ldb, const int B_multi_stride, + Tr *C, const int ldc, const int C_batch_stride, const int C_multi_stride) override + { + /* A and C's batch stride becomes their new row stride. New batch stride is 0 as nbatches for subgemm is always 1. */ + _subgemm->set_arrays(A, A_batch_stride, 0, A_multi_stride, + B, ldb, B_multi_stride, + C, C_batch_stride, 0, C_multi_stride); + } + + unsigned int get_window_size() const override + { + return _subgemm->get_window_size(); + } + + void set_nthreads(int nthreads) override + { + _subgemm->set_nthreads(nthreads); + } + + void execute(unsigned int start, unsigned int end, int threadid) override + { + _subgemm->execute(start, end, threadid); + } + + size_t get_working_size() const override + { + return _subgemm->get_working_size(); + } + + void set_working_space(void *space) override + { + _subgemm->set_working_space(space); + } + + bool B_is_pretransposed() const override + { + return _subgemm->B_is_pretransposed(); + } + + bool B_pretranspose_required() const override + { + return _subgemm->B_pretranspose_required(); + } + + size_t get_B_pretransposed_array_size() const override + { + return _subgemm->get_B_pretransposed_array_size(); + } + + void pretranspose_B_array(void *buffer, const To *B, const int ldb, const int B_multi_stride) override + { + _subgemm->pretranspose_B_array(buffer, B, ldb, B_multi_stride); + } + + void set_pretransposed_B_data(void *buffer) override + { + _subgemm->set_pretransposed_B_data(buffer); + } +}; + +} // namespace arm_gemm diff --git a/src/core/NEON/kernels/arm_gemm/kernels/a64_sgemm_native_16x4/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/a64_sgemm_native_16x4/generic.cpp index 8d4a38c36d..2b846c7f10 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/a64_sgemm_native_16x4/generic.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/a64_sgemm_native_16x4/generic.cpp @@ -23,7 +23,9 @@ */ #ifdef __aarch64__ +#include #include +#include #include @@ -35,22 +37,35 @@ void a64_sgemm_native_16x4(const float *A, int lda, const float *B, int ldb, flo const int beta0 = (beta == 0.0f) ? 1 : 0; const int oddones = (K % 4); + float dummy_buffer[16]; + + std::memset(dummy_buffer, 0, sizeof(dummy_buffer)); + /* For now, very naive with no blocking */ - for(int y = 0; y < M; y += 4) - { - for(int x0 = 0; x0 < N; x0 += 16) - { - const float *a_ptr0 = A + (y * lda); - const float *a_ptr1 = a_ptr0 + lda; - const float *a_ptr2 = a_ptr1 + lda; - const float *a_ptr3 = a_ptr2 + lda; + for (int y=0; y 1) ? (a_ptr0_base + lda) : dummy_buffer; + const float * const a_ptr2_base = (activerows > 2) ? (a_ptr1_base + lda) : dummy_buffer; + const float * const a_ptr3_base = (activerows > 3) ? (a_ptr2_base + lda) : dummy_buffer; + + const unsigned long a_incr1 = (activerows > 1) ? 32 : 0; + const unsigned long a_incr2 = (activerows > 2) ? 32 : 0; + const unsigned long a_incr3 = (activerows > 3) ? 32 : 0; - float *c_ptr0 = C + (y * ldc) + x0; - float *c_ptr1 = c_ptr0 + ldc; - float *c_ptr2 = c_ptr1 + ldc; - float *c_ptr3 = c_ptr2 + ldc; + float *c_ptr0 = C + (y * ldc); + float *c_ptr1 = (activerows > 1) ? c_ptr0 + ldc : dummy_buffer; + float *c_ptr2 = (activerows > 1) ? c_ptr1 + ldc : dummy_buffer; + float *c_ptr3 = (activerows > 1) ? c_ptr2 + ldc : dummy_buffer; + + for (int x0=0; x0