From d02d5edfa15ba6c04a9986a8a362a945cb38ac31 Mon Sep 17 00:00:00 2001
From: Michele Di Giorgio <michele.digiorgio@arm.com>
Date: Fri, 22 Jan 2021 09:47:04 +0000
Subject: Integrate improved CPU depthwise convolution kernels

* Replace assembly kernels for depthwise convolution with more optimized
  ones.
* Add int8 assembly kernels.
* Fix implicit padding on optimized kernels

Resolves: COMPMID-3867, COMPMID-4361

Change-Id: I0b0867e05f61be4f368f62190d55e14d0ab3ebf2
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5622
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
---
 src/core/NEON/kernels/arm_gemm/utils.hpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/core/NEON/kernels/arm_gemm/utils.hpp')

diff --git a/src/core/NEON/kernels/arm_gemm/utils.hpp b/src/core/NEON/kernels/arm_gemm/utils.hpp
index 6d483a3b9d..1269ef62a6 100644
--- a/src/core/NEON/kernels/arm_gemm/utils.hpp
+++ b/src/core/NEON/kernels/arm_gemm/utils.hpp
@@ -175,6 +175,18 @@ inline unsigned long get_vector_length() {
 #endif
 }
 
+template <typename T>
+inline unsigned long get_vector_length(VLType vl_type) {
+  switch (vl_type) {
+#ifdef __ARM_FEATURE_SVE
+    case VLType::SVE:
+      return get_vector_length_sz<sizeof(T)>();
+#endif
+    default:
+      return 16 / sizeof(T);
+  }
+}
+
 } // utils namespace
 } // arm_gemm namespace
 
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