From ba209750abc1ac7e42bab9fef5db284384d70fb3 Mon Sep 17 00:00:00 2001 From: Michael Tyler Date: Thu, 15 Dec 2022 12:39:29 +0000 Subject: Update CPU kernels to remove x19 Resolves: COMPMID-5805 Signed-off-by: Michael Tyler Change-Id: I250f64531e209625e4ff176dd5a552c1c34bc484 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8909 Tested-by: Arm Jenkins Comments-Addressed: Arm Jenkins Reviewed-by: Gunes Bayir Reviewed-by: Viet-Hoa Do Benchmark: Arm Jenkins --- .../sme_transpose_interleave_4VL_1x4.hpp | 60 +++++++++++----------- 1 file changed, 30 insertions(+), 30 deletions(-) (limited to 'src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp') diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp index 0429bb07fe..cbcc0b4c8b 100644 --- a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -10,16 +10,16 @@ * sell copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #pragma once @@ -43,44 +43,44 @@ void sme_transpose_interleave_4VL_1x4(uint8_t *out, const uint8_t *in, size_t wi ".inst 0xd503477f // SMSTART ZA\n" "ptrue p1.b\n" "1:" // Main row loop: Head - "mov x24, %x[in]\n" + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" "add x23, x24, %x[in_stride]\n" "add x22, x23, %x[in_stride]\n" - "add x21, x22, %x[in_stride]\n" "cmp %x[height], #0x3\n" - "add %x[in], x21, %x[in_stride]\n" - "csel x21, x21, %x[pad_row], GT\n" - "csel x22, x22, %x[pad_row], GE\n" + "add %x[in], x22, %x[in_stride]\n" + "csel x22, x22, %x[pad_row], GT\n" + "csel x23, x23, %x[pad_row], GE\n" "cmp %x[height], #0x1\n" - "mov x20, %x[out]\n" - "csel x23, x23, %x[pad_row], GT\n" + "mov x21, %x[out]\n" + "csel x24, x24, %x[pad_row], GT\n" "sub %x[height], %x[height], #0x4\n" - "mov x19, %x[width]\n" + "mov x20, %x[width]\n" "2:" // Main row loop: Column loop - "whilelt p0.b, XZR, x19\n" - "ld1b { z17.b }, p0/Z, [x24]\n" - "decw x19, ALL, MUL #4\n" - "ld1b { z19.b }, p0/Z, [x23]\n" - "cmp x19, #0x0\n" - "addvl x24, x24, #1\n" - "ld1b { z16.b }, p0/Z, [x22]\n" + "whilelt p0.b, XZR, x20\n" + "ld1b { z17.b }, p0/Z, [x25]\n" + "decw x20, ALL, MUL #4\n" + "ld1b { z19.b }, p0/Z, [x24]\n" + "cmp x20, #0x0\n" + "addvl x25, x25, #1\n" + "ld1b { z16.b }, p0/Z, [x23]\n" "zip1 z18.b, z17.b, z16.b\n" "zip2 z20.b, z17.b, z16.b\n" - "addvl x23, x23, #1\n" - "ld1b { z16.b }, p0/Z, [x21]\n" + "addvl x24, x24, #1\n" + "ld1b { z16.b }, p0/Z, [x22]\n" "zip1 z17.b, z19.b, z16.b\n" "zip2 z19.b, z19.b, z16.b\n" + "addvl x23, x23, #1\n" "addvl x22, x22, #1\n" - "addvl x21, x21, #1\n" "zip1 z16.b, z18.b, z17.b\n" "zip2 z18.b, z18.b, z17.b\n" - "st1b { z16.b }, p1, [x20]\n" + "st1b { z16.b }, p1, [x21]\n" "zip1 z17.b, z20.b, z19.b\n" "zip2 z16.b, z20.b, z19.b\n" - "st1b { z18.b }, p1, [x20, #1, MUL VL]\n" - "st1b { z17.b }, p1, [x20, #2, MUL VL]\n" - "st1b { z16.b }, p1, [x20, #3, MUL VL]\n" - "add x20, x20, %x[out_stride]\n" + "st1b { z18.b }, p1, [x21, #1, MUL VL]\n" + "st1b { z17.b }, p1, [x21, #2, MUL VL]\n" + "st1b { z16.b }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" "bgt 2b\n" "3:" // Main row loop: Column loop skip "cmp %x[height], #0x1\n" @@ -89,7 +89,7 @@ void sme_transpose_interleave_4VL_1x4(uint8_t *out, const uint8_t *in, size_t wi ".inst 0xd503467f // SMSTOP\n" : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } -- cgit v1.2.1