From 74921eee924625426429044decefe3673561b174 Mon Sep 17 00:00:00 2001 From: Michael Tyler Date: Wed, 12 Apr 2023 17:43:17 +0100 Subject: Update CPU kernel implementations and guard directives Resolves COMPMID-6023 Change-Id: I868975d14c4f98af6716726feda22405a6a4c891 Signed-off-by: Michael Tyler Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686 Tested-by: Arm Jenkins Reviewed-by: Viet-Hoa Do Comments-Addressed: Arm Jenkins Benchmark: Arm Jenkins --- .../sve_ffinterleaved_fp32_mla_8x3VL/a64fx.cpp | 194 ++++++++++----------- 1 file changed, 97 insertions(+), 97 deletions(-) (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/a64fx.cpp') diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/a64fx.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/a64fx.cpp index 8c8b6b0675..c65c3a3ce4 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/a64fx.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/a64fx.cpp @@ -52,33 +52,33 @@ void sve_ffinterleaved_fp32_mla_8x3VL_a64fx( __asm__ __volatile__( "ptrue p0.b\n" "1:" // Height loop - "ldr x26, [%x[args_ptr], %[offsetof_Bpanel]]\n" - "ldr x25, [%x[args_ptr], %[offsetof_N]]\n" - "str x26, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" - "mov x24, %x[Apanel]\n" + "ldr x20, [%x[args_ptr], %[offsetof_Bpanel]]\n" + "ldr x26, [%x[args_ptr], %[offsetof_N]]\n" + "str x20, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" + "mov x25, %x[Apanel]\n" "2:" // Width loop - "ldr x26, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" + "ldr x24, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" "ldr x20, [%x[args_ptr], %[offsetof_B_stride]]\n" "cntw x23, ALL, MUL #2\n" - "add x22, x26, x20, LSL #2\n" + "add x22, x24, x20, LSL #2\n" "add x21, x22, x20, LSL #2\n" "add x20, x21, x20, LSL #2\n" - "cmp x25, x23\n" + "cmp x26, x23\n" "str x20, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" - "mov %x[Apanel], x24\n" + "mov %x[Apanel], x25\n" "bgt 3f\n" "decw x23\n" - "cmp x25, x23\n" - "mov x21, x26\n" + "cmp x26, x23\n" + "mov x21, x24\n" "bgt 3f\n" - "mov x22, x26\n" + "mov x22, x24\n" "3:" // B setup done "ldr x20, [%x[args_ptr], %[offsetof_K]]\n" "cmp x20, #0x2\n" "mov z8.b, #0x0\n" "mov z9.b, #0x0\n" "mov z10.b, #0x0\n" - "ld1w { z0.s }, p0/Z, [x26]\n" + "ld1w { z0.s }, p0/Z, [x24]\n" "mov z11.b, #0x0\n" "mov z12.b, #0x0\n" "ld1w { z1.s }, p0/Z, [x22]\n" @@ -116,12 +116,12 @@ void sve_ffinterleaved_fp32_mla_8x3VL_a64fx( "fmla z11.s, p0/M, z0.s, z4.s\n" "fmla z12.s, p0/M, z1.s, z4.s\n" "fmla z13.s, p0/M, z2.s, z4.s\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #20]\n" "fmla z14.s, p0/M, z0.s, z5.s\n" "fmla z15.s, p0/M, z1.s, z5.s\n" "cmp x20, #0x2\n" "fmla z16.s, p0/M, z2.s, z5.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #24]\n" + "ld1rw { z4.s }, p0/Z, [%x[Apanel], #24]\n" "fmla z17.s, p0/M, z0.s, z6.s\n" "fmla z18.s, p0/M, z1.s, z6.s\n" "fmla z19.s, p0/M, z2.s, z6.s\n" @@ -130,57 +130,57 @@ void sve_ffinterleaved_fp32_mla_8x3VL_a64fx( "fmla z21.s, p0/M, z1.s, z3.s\n" "fmla z22.s, p0/M, z2.s, z3.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel], #32]\n" - "fmla z23.s, p0/M, z0.s, z4.s\n" - "fmla z24.s, p0/M, z1.s, z4.s\n" - "fmla z25.s, p0/M, z2.s, z4.s\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #36]\n" - "fmla z26.s, p0/M, z0.s, z5.s\n" - "fmla z27.s, p0/M, z1.s, z5.s\n" - "fmla z28.s, p0/M, z2.s, z5.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #40]\n" + "fmla z23.s, p0/M, z0.s, z7.s\n" + "fmla z24.s, p0/M, z1.s, z7.s\n" + "fmla z25.s, p0/M, z2.s, z7.s\n" + "ld1rw { z5.s }, p0/Z, [%x[Apanel], #36]\n" + "fmla z26.s, p0/M, z0.s, z4.s\n" + "fmla z27.s, p0/M, z1.s, z4.s\n" + "fmla z28.s, p0/M, z2.s, z4.s\n" + "ld1rw { z4.s }, p0/Z, [%x[Apanel], #40]\n" "fmla z29.s, p0/M, z0.s, z6.s\n" - "ld1w { z0.s }, p0/Z, [x26, #1, MUL VL]\n" + "ld1w { z7.s }, p0/Z, [x24, #1, MUL VL]\n" "fmla z30.s, p0/M, z1.s, z6.s\n" "fmla z31.s, p0/M, z2.s, z6.s\n" - "ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n" + "ld1w { z6.s }, p0/Z, [x22, #1, MUL VL]\n" "ld1w { z2.s }, p0/Z, [x21, #1, MUL VL]\n" - "fmla z8.s, p0/M, z0.s, z3.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #44]\n" - "fmla z9.s, p0/M, z1.s, z3.s\n" + "fmla z8.s, p0/M, z7.s, z3.s\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #44]\n" + "fmla z9.s, p0/M, z6.s, z3.s\n" "fmla z10.s, p0/M, z2.s, z3.s\n" - "fmla z11.s, p0/M, z0.s, z4.s\n" + "fmla z11.s, p0/M, z7.s, z5.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel], #48]\n" - "fmla z12.s, p0/M, z1.s, z4.s\n" - "fmla z13.s, p0/M, z2.s, z4.s\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #52]\n" - "fmla z14.s, p0/M, z0.s, z5.s\n" - "fmla z15.s, p0/M, z1.s, z5.s\n" - "addvl x26, x26, #2\n" - "fmla z16.s, p0/M, z2.s, z5.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #56]\n" - "fmla z17.s, p0/M, z0.s, z6.s\n" - "fmla z18.s, p0/M, z1.s, z6.s\n" - "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #60]\n" + "fmla z12.s, p0/M, z6.s, z5.s\n" + "fmla z13.s, p0/M, z2.s, z5.s\n" + "ld1rw { z5.s }, p0/Z, [%x[Apanel], #52]\n" + "fmla z14.s, p0/M, z7.s, z4.s\n" + "fmla z15.s, p0/M, z6.s, z4.s\n" + "addvl x24, x24, #2\n" + "fmla z16.s, p0/M, z2.s, z4.s\n" + "ld1rw { z0.s }, p0/Z, [%x[Apanel], #56]\n" + "fmla z17.s, p0/M, z7.s, z1.s\n" + "fmla z18.s, p0/M, z6.s, z1.s\n" + "fmla z19.s, p0/M, z2.s, z1.s\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #60]\n" "addvl x22, x22, #2\n" "addvl x21, x21, #2\n" "add %x[Apanel], %x[Apanel], #0x40\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" + "fmla z20.s, p0/M, z7.s, z3.s\n" + "fmla z21.s, p0/M, z6.s, z3.s\n" "fmla z22.s, p0/M, z2.s, z3.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" - "fmla z23.s, p0/M, z0.s, z4.s\n" - "fmla z24.s, p0/M, z1.s, z4.s\n" - "fmla z25.s, p0/M, z2.s, z4.s\n" - "fmla z26.s, p0/M, z0.s, z5.s\n" + "fmla z23.s, p0/M, z7.s, z5.s\n" + "fmla z24.s, p0/M, z6.s, z5.s\n" + "fmla z25.s, p0/M, z2.s, z5.s\n" + "fmla z26.s, p0/M, z7.s, z0.s\n" "ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n" - "fmla z27.s, p0/M, z1.s, z5.s\n" - "fmla z28.s, p0/M, z2.s, z5.s\n" + "fmla z27.s, p0/M, z6.s, z0.s\n" + "fmla z28.s, p0/M, z2.s, z0.s\n" "ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" - "ld1w { z0.s }, p0/Z, [x26]\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" + "fmla z29.s, p0/M, z7.s, z1.s\n" + "ld1w { z0.s }, p0/Z, [x24]\n" + "fmla z30.s, p0/M, z6.s, z1.s\n" + "fmla z31.s, p0/M, z2.s, z1.s\n" "ld1w { z1.s }, p0/Z, [x22]\n" "ld1w { z2.s }, p0/Z, [x21]\n" "ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n" @@ -188,9 +188,9 @@ void sve_ffinterleaved_fp32_mla_8x3VL_a64fx( "5:" // main loop skip "fmla z8.s, p0/M, z0.s, z3.s\n" "fmla z9.s, p0/M, z1.s, z3.s\n" - "addvl x26, x26, #1\n" + "addvl x24, x24, #1\n" "fmla z10.s, p0/M, z2.s, z3.s\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #16]\n" "fmla z11.s, p0/M, z0.s, z4.s\n" "fmla z12.s, p0/M, z1.s, z4.s\n" "fmla z13.s, p0/M, z2.s, z4.s\n" @@ -203,11 +203,11 @@ void sve_ffinterleaved_fp32_mla_8x3VL_a64fx( "fmla z17.s, p0/M, z0.s, z6.s\n" "fmla z18.s, p0/M, z1.s, z6.s\n" "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #28]\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" + "ld1rw { z3.s }, p0/Z, [%x[Apanel], #28]\n" + "fmla z20.s, p0/M, z0.s, z7.s\n" + "fmla z21.s, p0/M, z1.s, z7.s\n" "addvl x21, x21, #1\n" - "fmla z22.s, p0/M, z2.s, z3.s\n" + "fmla z22.s, p0/M, z2.s, z7.s\n" "fmla z23.s, p0/M, z0.s, z4.s\n" "add %x[Apanel], %x[Apanel], #0x20\n" "fmla z24.s, p0/M, z1.s, z4.s\n" @@ -215,50 +215,50 @@ void sve_ffinterleaved_fp32_mla_8x3VL_a64fx( "fmla z26.s, p0/M, z0.s, z5.s\n" "fmla z27.s, p0/M, z1.s, z5.s\n" "fmla z28.s, p0/M, z2.s, z5.s\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" + "fmla z29.s, p0/M, z0.s, z3.s\n" + "fmla z30.s, p0/M, z1.s, z3.s\n" + "fmla z31.s, p0/M, z2.s, z3.s\n" "cbz x20, 6f\n" - "ld1w { z0.s }, p0/Z, [x26]\n" - "ld1w { z1.s }, p0/Z, [x22]\n" - "ld1w { z2.s }, p0/Z, [x21]\n" + "ld1w { z6.s }, p0/Z, [x24]\n" + "ld1w { z5.s }, p0/Z, [x22]\n" + "ld1w { z4.s }, p0/Z, [x21]\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" - "fmla z8.s, p0/M, z0.s, z3.s\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n" - "fmla z9.s, p0/M, z1.s, z3.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n" - "fmla z10.s, p0/M, z2.s, z3.s\n" - "fmla z11.s, p0/M, z0.s, z4.s\n" - "fmla z12.s, p0/M, z1.s, z4.s\n" - "fmla z13.s, p0/M, z2.s, z4.s\n" + "fmla z8.s, p0/M, z6.s, z3.s\n" + "ld1rw { z2.s }, p0/Z, [%x[Apanel], #4]\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #8]\n" + "fmla z9.s, p0/M, z5.s, z3.s\n" + "ld1rw { z0.s }, p0/Z, [%x[Apanel], #12]\n" + "fmla z10.s, p0/M, z4.s, z3.s\n" + "fmla z11.s, p0/M, z6.s, z2.s\n" + "fmla z12.s, p0/M, z5.s, z2.s\n" + "fmla z13.s, p0/M, z4.s, z2.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" - "fmla z14.s, p0/M, z0.s, z5.s\n" - "fmla z15.s, p0/M, z1.s, z5.s\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #20]\n" - "fmla z16.s, p0/M, z2.s, z5.s\n" - "fmla z17.s, p0/M, z0.s, z6.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #24]\n" - "fmla z18.s, p0/M, z1.s, z6.s\n" - "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #28]\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" + "fmla z14.s, p0/M, z6.s, z1.s\n" + "fmla z15.s, p0/M, z5.s, z1.s\n" + "ld1rw { z2.s }, p0/Z, [%x[Apanel], #20]\n" + "fmla z16.s, p0/M, z4.s, z1.s\n" + "fmla z17.s, p0/M, z6.s, z0.s\n" + "ld1rw { z1.s }, p0/Z, [%x[Apanel], #24]\n" + "fmla z18.s, p0/M, z5.s, z0.s\n" + "fmla z19.s, p0/M, z4.s, z0.s\n" + "ld1rw { z0.s }, p0/Z, [%x[Apanel], #28]\n" + "fmla z20.s, p0/M, z6.s, z3.s\n" + "fmla z21.s, p0/M, z5.s, z3.s\n" "add %x[Apanel], %x[Apanel], #0x20\n" - "fmla z22.s, p0/M, z2.s, z3.s\n" - "fmla z23.s, p0/M, z0.s, z4.s\n" - "fmla z24.s, p0/M, z1.s, z4.s\n" - "fmla z25.s, p0/M, z2.s, z4.s\n" - "fmla z26.s, p0/M, z0.s, z5.s\n" - "fmla z27.s, p0/M, z1.s, z5.s\n" - "fmla z28.s, p0/M, z2.s, z5.s\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" + "fmla z22.s, p0/M, z4.s, z3.s\n" + "fmla z23.s, p0/M, z6.s, z2.s\n" + "fmla z24.s, p0/M, z5.s, z2.s\n" + "fmla z25.s, p0/M, z4.s, z2.s\n" + "fmla z26.s, p0/M, z6.s, z1.s\n" + "fmla z27.s, p0/M, z5.s, z1.s\n" + "fmla z28.s, p0/M, z4.s, z1.s\n" + "fmla z29.s, p0/M, z6.s, z0.s\n" + "fmla z30.s, p0/M, z5.s, z0.s\n" + "fmla z31.s, p0/M, z4.s, z0.s\n" "6:" // multiply loop done - "decw x25, ALL, MUL #3\n" + "decw x26, ALL, MUL #3\n" "st1w { z8.s }, p0, [%x[Cpanel]]\n" - "cmp x25, XZR\n" + "cmp x26, XZR\n" "st1w { z9.s }, p0, [%x[Cpanel], #1, MUL VL]\n" "st1w { z10.s }, p0, [%x[Cpanel], #2, MUL VL]\n" "st1w { z11.s }, p0, [%x[Cpanel], #3, MUL VL]\n" @@ -289,7 +289,7 @@ void sve_ffinterleaved_fp32_mla_8x3VL_a64fx( "bne 1b\n" : [Apanel] "+&r" (Apanel), [Cpanel] "+&r" (Cpanel), [ablocks] "+&r" (ablocks) : [args_ptr] "r" (&ka), [offsetof_B_stride] "I" (offsetof(KernelArgs, B_stride)), [offsetof_Bpanel] "I" (offsetof(KernelArgs, Bpanel)), [offsetof_K] "I" (offsetof(KernelArgs, K)), [offsetof_N] "I" (offsetof(KernelArgs, N)), [offsetof_cur_B_ptr] "I" (offsetof(KernelArgs, cur_B_ptr)) - : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } -- cgit v1.2.1