From e28cf395b57a091d0850cd28cecc81046153b843 Mon Sep 17 00:00:00 2001 From: Georgios Pinitas Date: Sun, 31 Jan 2021 05:18:43 +0000 Subject: Regenerate kernels and update A55 versions Signed-off-by: Georgios Pinitas Change-Id: I9eae76c77db03b8806af65729da34ab2d77f95f2 Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4965 Tested-by: Arm Jenkins Reviewed-by: Michele Di Giorgio Comments-Addressed: Arm Jenkins --- .../a64_interleave8_block1_bf16_fp32.hpp | 156 ++++++++++----------- 1 file changed, 78 insertions(+), 78 deletions(-) (limited to 'src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp') diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp index 34d25f27b8..42574295f1 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020 Arm Limited. + * Copyright (c) 2019-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -31,7 +31,7 @@ void interleave_block<8, 1, VLType::None, false>( ) { __asm__ __volatile__( - "movi v29.8h, #0x0\n" + "movi v30.8h, #0x0\n" "ldr x27, [%x[in], #0x0]\n" "cmp %x[height], #0x8\n" "ldr x26, [%x[in], #0x8]\n" @@ -80,53 +80,53 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x20, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr d28, [x27], #0x8\n" - "zip1 v28.8h, v29.8h, v28.8h\n" + "ldr d29, [x27], #0x8\n" + "zip1 v29.8h, v30.8h, v29.8h\n" + "ldr d28, [x26], #0x8\n" + "subs %x[width], %x[width], #0x4\n" + "zip1 v28.8h, v30.8h, v28.8h\n" + "ldr d24, [x25], #0x8\n" + "cmp %x[width], #0x4\n" + "zip1 v24.8h, v30.8h, v24.8h\n" + "ldr d27, [x24], #0x8\n" + "ldr d26, [x23], #0x8\n" + "zip1 v25.4s, v29.4s, v24.4s\n" + "zip2 v24.4s, v29.4s, v24.4s\n" + "ldr d23, [x22], #0x8\n" + "ldr d22, [x21], #0x8\n" + "zip1 v27.8h, v30.8h, v27.8h\n" + "ldr d21, [x20], #0x8\n" + "zip1 v26.8h, v30.8h, v26.8h\n" "prfm pldl1keep, [x27, #0x70]\n" - "ldr d27, [x26], #0x8\n" - "zip1 v27.8h, v29.8h, v27.8h\n" + "zip1 v20.4s, v28.4s, v27.4s\n" "prfm pldl1keep, [x26, #0x70]\n" - "ldr d26, [x25], #0x8\n" - "zip1 v26.8h, v29.8h, v26.8h\n" + "zip1 v23.8h, v30.8h, v23.8h\n" "prfm pldl1keep, [x25, #0x70]\n" - "ldr d25, [x24], #0x8\n" - "zip1 v20.4s, v28.4s, v26.4s\n" + "zip1 v22.8h, v30.8h, v22.8h\n" "prfm pldl1keep, [x24, #0x70]\n" - "zip1 v25.8h, v29.8h, v25.8h\n" - "ldr d24, [x23], #0x8\n" - "zip1 v19.4s, v27.4s, v25.4s\n" + "zip1 v21.8h, v30.8h, v21.8h\n" "prfm pldl1keep, [x23, #0x70]\n" - "zip1 v24.8h, v29.8h, v24.8h\n" - "ldr d23, [x22], #0x8\n" - "zip1 v16.4s, v20.4s, v19.4s\n" + "zip1 v17.4s, v25.4s, v20.4s\n" "prfm pldl1keep, [x22, #0x70]\n" - "zip1 v23.8h, v29.8h, v23.8h\n" - "ldr d22, [x21], #0x8\n" - "zip2 v19.4s, v20.4s, v19.4s\n" + "zip1 v19.4s, v26.4s, v22.4s\n" "prfm pldl1keep, [x21, #0x70]\n" - "zip1 v22.8h, v29.8h, v22.8h\n" - "ldr d21, [x20], #0x8\n" - "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v18.4s, v23.4s, v21.4s\n" "prfm pldl1keep, [x20, #0x70]\n" - "zip1 v21.8h, v29.8h, v21.8h\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v17.4s, v23.4s, v21.4s\n" - "subs %x[width], %x[width], #0x4\n" - "zip2 v20.4s, v28.4s, v26.4s\n" - "cmp %x[width], #0x4\n" - "zip1 v16.4s, v18.4s, v17.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.4s, v25.4s, v20.4s\n" "str q16, [%x[out_ptr], #0x10]\n" - "zip2 v16.4s, v18.4s, v17.4s\n" - "str q19, [%x[out_ptr], #0x20]\n" - "zip2 v19.4s, v27.4s, v25.4s\n" + "zip2 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x20]\n" + "zip2 v19.4s, v28.4s, v27.4s\n" "str q16, [%x[out_ptr], #0x30]\n" - "zip1 v16.4s, v20.4s, v19.4s\n" + "zip1 v16.4s, v24.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x40]\n" - "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v18.4s, v26.4s, v22.4s\n" "zip2 v17.4s, v23.4s, v21.4s\n" "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x50]\n" - "zip2 v16.4s, v20.4s, v19.4s\n" + "zip2 v16.4s, v24.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x60]\n" "zip2 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x70]\n" @@ -135,77 +135,77 @@ void interleave_block<8, 1, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 6f\n" "tbz %x[width], #1, 4f\n" - "ldr s28, [x27], #0x4\n" - "ldr s27, [x26], #0x4\n" - "ldr s26, [x25], #0x4\n" - "ldr s25, [x24], #0x4\n" - "ldr s24, [x23], #0x4\n" + "ldr s29, [x27], #0x4\n" + "ldr s28, [x26], #0x4\n" + "mov x19, #0x2\n" + "ldr s24, [x25], #0x4\n" + "ldr s27, [x24], #0x4\n" + "ldr s26, [x23], #0x4\n" "ldr s23, [x22], #0x4\n" "ldr s22, [x21], #0x4\n" "ldr s21, [x20], #0x4\n" - "mov x19, #0x2\n" "tbz %x[width], #0, 5f\n" - "ld1 { v28.h }[2], [x27]\n" - "ld1 { v27.h }[2], [x26]\n" - "ld1 { v26.h }[2], [x25]\n" - "ld1 { v25.h }[2], [x24]\n" - "ld1 { v24.h }[2], [x23]\n" + "ld1 { v29.h }[2], [x27]\n" + "mov x19, #0x3\n" + "ld1 { v28.h }[2], [x26]\n" + "ld1 { v24.h }[2], [x25]\n" + "ld1 { v27.h }[2], [x24]\n" + "ld1 { v26.h }[2], [x23]\n" "ld1 { v23.h }[2], [x22]\n" "ld1 { v22.h }[2], [x21]\n" "ld1 { v21.h }[2], [x20]\n" - "mov x19, #0x3\n" "b 5f\n" "4:" // odd_loads_1_0 - "ldr h28, [x27, #0x0]\n" - "ldr h27, [x26, #0x0]\n" - "ldr h26, [x25, #0x0]\n" - "ldr h25, [x24, #0x0]\n" - "ldr h24, [x23, #0x0]\n" + "ldr h29, [x27, #0x0]\n" + "mov x19, #0x1\n" + "ldr h28, [x26, #0x0]\n" + "ldr h24, [x25, #0x0]\n" + "ldr h27, [x24, #0x0]\n" + "ldr h26, [x23, #0x0]\n" "ldr h23, [x22, #0x0]\n" "ldr h22, [x21, #0x0]\n" "ldr h21, [x20, #0x0]\n" - "mov x19, #0x1\n" "5:" // Odd load end - "zip1 v28.8h, v29.8h, v28.8h\n" + "zip1 v29.8h, v30.8h, v29.8h\n" "subs x19, x19, #0x1\n" - "zip1 v27.8h, v29.8h, v27.8h\n" - "zip1 v26.8h, v29.8h, v26.8h\n" - "zip1 v25.8h, v29.8h, v25.8h\n" - "zip1 v24.8h, v29.8h, v24.8h\n" - "zip1 v23.8h, v29.8h, v23.8h\n" - "zip1 v22.8h, v29.8h, v22.8h\n" - "zip1 v21.8h, v29.8h, v21.8h\n" - "zip1 v20.4s, v28.4s, v26.4s\n" - "zip1 v19.4s, v27.4s, v25.4s\n" - "zip1 v16.4s, v20.4s, v19.4s\n" - "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v24.4s, v22.4s\n" - "zip1 v17.4s, v23.4s, v21.4s\n" - "zip1 v16.4s, v18.4s, v17.4s\n" + "zip1 v28.8h, v30.8h, v28.8h\n" + "zip1 v24.8h, v30.8h, v24.8h\n" + "zip1 v27.8h, v30.8h, v27.8h\n" + "zip1 v26.8h, v30.8h, v26.8h\n" + "zip1 v23.8h, v30.8h, v23.8h\n" + "zip1 v22.8h, v30.8h, v22.8h\n" + "zip1 v21.8h, v30.8h, v21.8h\n" + "zip1 v25.4s, v29.4s, v24.4s\n" + "zip1 v20.4s, v28.4s, v27.4s\n" + "zip1 v17.4s, v25.4s, v20.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip1 v19.4s, v26.4s, v22.4s\n" + "zip1 v18.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v19.4s, v20.4s, v19.4s\n" - "zip2 v16.4s, v18.4s, v17.4s\n" - "str q19, [%x[out_ptr], #0x0]\n" - "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v17.4s, v25.4s, v20.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v19.4s, v18.4s\n" "subs x19, x19, #0x1\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v20.4s, v28.4s, v26.4s\n" - "zip2 v19.4s, v27.4s, v25.4s\n" - "zip1 v16.4s, v20.4s, v19.4s\n" + "zip2 v24.4s, v29.4s, v24.4s\n" + "zip2 v19.4s, v28.4s, v27.4s\n" + "zip1 v16.4s, v24.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v18.4s, v26.4s, v22.4s\n" "zip2 v17.4s, v23.4s, v21.4s\n" "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "6:" // Odds skip - : [out_ptr] "+r" (out_ptr), [width] "+r" (width) + : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } -- cgit v1.2.1