From 20fca524baf99402f742ce38c538f2fd07d5fff9 Mon Sep 17 00:00:00 2001 From: Michalis Spyrou Date: Mon, 7 Jun 2021 14:23:57 +0100 Subject: Create core library using high priority operators A smaller core library is created using a subset of the operators. Changed the structure of filelist.json in order to include more information about the kernels and make the selection easier. Resolves: COMPMID-4514 Change-Id: I079ca7d8e64346174eebdd13b834e1dd4dc36ca2 Signed-off-by: Michalis Spyrou Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5786 Tested-by: Arm Jenkins Reviewed-by: Georgios Pinitas Comments-Addressed: Arm Jenkins --- src/core/NEON/kernels/arm_gemm/gemm_quint8.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/core/NEON/kernels/arm_gemm/gemm_quint8.cpp') diff --git a/src/core/NEON/kernels/arm_gemm/gemm_quint8.cpp b/src/core/NEON/kernels/arm_gemm/gemm_quint8.cpp index be27b3a117..f3f2f335fd 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_quint8.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_quint8.cpp @@ -50,12 +50,12 @@ namespace arm_gemm { static const GemmImplementation gemm_quint8_methods[] = { -#ifdef __ARM_FEATURE_SVE -#ifdef MMLA_INT8 +#ifdef ARM_COMPUTE_ENABLE_SVE +#ifdef ARM_COMPUTE_ENABLE_I8MM { GemmMethod::GEMM_INTERLEAVED, "sve_interleaved_u8u32_mmla_8x3VL", - [](const GemmArgs &args, const Requantize32 &) { return args._ci->has_sve() && (args._Ksize>8); }, + [](const GemmArgs &args, const Requantize32 &) { return args._ci->has_svei8mm() && (args._Ksize>8); }, [](const GemmArgs &args, const Requantize32 &) { return args._ci->get_cpu_model() != CPUModel::KLEIN; }, [](const GemmArgs &args, const Requantize32 &qp) { return new GemmInterleavedQuantized(args, qp); } }, @@ -67,15 +67,15 @@ static const GemmImplementation gemm_quint8_meth [](const GemmArgs &args, const Requantize32 &) { return args._ci->get_cpu_model() != CPUModel::KLEIN; }, [](const GemmArgs &args, const Requantize32 &qp) { return new GemmHybridQuantized(args, qp); } }, -#ifdef SVE2 // Requantizing kernels include some SVE2 only instructions (SQRDMULH, SRSHL) +#ifdef ARM_COMPUTE_ENABLE_SVE2 // Requantizing kernels include some SVE2 only instructions (SQRDMULH, SRSHL) { GemmMethod::GEMM_HYBRID, "sve_hybrid_u8qa_dot_4x4VL", - [](const GemmArgs &args, const Requantize32 &qp) { return args._ci->has_sve() && quant_hybrid_asymmetric(qp); }, + [](const GemmArgs &args, const Requantize32 &qp) { return args._ci->has_sve2() && quant_hybrid_asymmetric(qp); }, [](const GemmArgs &args, const Requantize32 &) { return args._ci->get_cpu_model() != CPUModel::KLEIN; }, [](const GemmArgs &args, const Requantize32 &qp) { return new GemmHybridIndirect(args, qp); } }, -#endif +#endif // ARM_COMPUTE_ENABLE_SVE2 { GemmMethod::GEMM_HYBRID, "sve_hybrid_u8u32_dot_6x4VL", @@ -91,11 +91,11 @@ static const GemmImplementation gemm_quint8_meth [](const GemmArgs &args, const Requantize32 &qp) { return new GemmInterleavedQuantized(args, qp); } }, #endif -#ifdef MMLA_INT8 +#ifdef ARM_COMPUTE_ENABLE_I8MM { GemmMethod::GEMM_INTERLEAVED, "a64_interleaved_u8u32_mmla_8x12", - [](const GemmArgs &args, const Requantize32 &) { return (args._Ksize>8); }, + [](const GemmArgs &args, const Requantize32 &) { return args._ci->has_i8mm() && (args._Ksize>8); }, [](const GemmArgs &args, const Requantize32 &) { return args._ci->get_cpu_model() != CPUModel::KLEIN; }, [](const GemmArgs &args, const Requantize32 &qp) { return new GemmInterleavedQuantized(args, qp); } }, -- cgit v1.2.1