From e7e96e09ff0d3e47797adf197aff2bc39671788c Mon Sep 17 00:00:00 2001 From: Michalis Spyrou Date: Fri, 13 Apr 2018 13:44:10 +0100 Subject: COMPMID-1054 Update RSH's GEMM to add batch+multi support Change-Id: Ib9d91b77f1d51976da4449fa1e6eeeffae307353 Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/127876 Tested-by: Jenkins Reviewed-by: Pablo Tello Reviewed-by: Anthony Barbier --- src/core/NEON/kernels/arm_gemm/gemm_int8.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/core/NEON/kernels/arm_gemm/gemm_int8.cpp') diff --git a/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp b/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp index 856d407cfa..f13406284c 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_int8.cpp @@ -35,16 +35,17 @@ namespace arm_gemm { template <> UniqueGemmCommon gemm(const CPUInfo &ci, const unsigned int M, const unsigned int N, const unsigned int K, + const unsigned int nbatches, const unsigned int nmulti, const bool trA, const bool trB, const int32_t alpha, const int32_t beta, const int maxthreads, const bool pretransposed_hint) { if(ci.has_dotprod()) { // Dot product supporting CPUs. This family has a special version for A55r1. - return UniqueGemmCommon(new GemmInterleaved(&ci, M, N, K, trA, trB, alpha, beta, maxthreads, pretransposed_hint)); + return UniqueGemmCommon(new GemmInterleaved(&ci, M, N, K, nbatches, nmulti, trA, trB, alpha, beta, maxthreads, pretransposed_hint)); } - return UniqueGemmCommon(new GemmInterleaved(&ci, M, N, K, trA, trB, alpha, beta, maxthreads, pretransposed_hint)); + return UniqueGemmCommon(new GemmInterleaved(&ci, M, N, K, nbatches, nmulti, trA, trB, alpha, beta, maxthreads, pretransposed_hint)); // TODO: There's a better approach for A53, but it doesn't work // well on heterogeneous systems as the required data formats -- cgit v1.2.1